📄 fpga_dsp_portlink.sim.rpt
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; |FPGA_DSP_PortLink_BiBus_oneFIFO|en_blk:inst8|To_DSP_En~19 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|en_blk:inst8|To_DSP_En~19 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~524 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~524 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~73 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~73 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~75 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~75 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~0 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~0 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~526 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~526 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_rdreq~29 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_rdreq~29 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdcnt_addr_ena ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdcnt_addr_ena ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_wrreq ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_wrreq ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_rdreq ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|valid_rdreq ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|parity_ff ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|parity_ff ; regout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|parity ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|parity ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|parity ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|parity~COUT ; cout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera0 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera0 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera0 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera0~COUT ; cout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera1 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera1 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera1 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera1~COUT ; cout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera2 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|countera2 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|parity_ff ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|parity_ff ; regout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|parity ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|parity ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|parity ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|parity~COUT ; cout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera0 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera0 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera0 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera0~COUT ; cout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera1 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|countera1 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|Addr[1] ; |FPGA_DSP_PortLink_BiBus_oneFIFO|Addr[1] ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|Addr[0] ; |FPGA_DSP_PortLink_BiBus_oneFIFO|Addr[0] ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|CS ; |FPGA_DSP_PortLink_BiBus_oneFIFO|CS ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|RE ; |FPGA_DSP_PortLink_BiBus_oneFIFO|RE ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|WE ; |FPGA_DSP_PortLink_BiBus_oneFIFO|WE ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~8 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~8 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~8 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP[7]~output ; padio ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~10 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~10 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~10 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP[5]~output ; padio ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~11 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~11 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~14 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~14 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~15 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~15 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP~15 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|TO_DSP[0]~output ; padio ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|en_blk:inst8|To_DSP_En~19clkctrl ; |FPGA_DSP_PortLink_BiBus_oneFIFO|en_blk:inst8|To_DSP_En~19clkctrl ; outclk ;
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The following table displays output ports that do not toggle to 1 during simulation.
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; Missing 1-Value Coverage ;
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; Node Name ; Output Port Name ; Output Port Type ;
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; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~510 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~510 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~511 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~511 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~512 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~512 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~513 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~513 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[11] ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[11] ; portadataout0 ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[11] ; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[15] ; portadataout1 ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~514 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~514 ; combout ;
; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~515 ; |FPGA_DSP_PortLink_BiBus_oneFIFO|MUX:inst10|O1~515 ; combout ;
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