fpga_dsp_portlink.sim.rpt

来自「implemention of FPGA and DSP linking por」· RPT 代码 · 共 277 行 · 第 1/5 页

+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                                              ;
+-----------------------------------------------------------------+---------------------------------------------------------------+---------------+
; Option                                                          ; Setting                                                       ; Default Value ;
+-----------------------------------------------------------------+---------------------------------------------------------------+---------------+
; Simulation mode                                                 ; Timing                                                        ; Timing        ;
; Start time                                                      ; 0 ns                                                          ; 0 ns          ;
; Vector input source                                             ; E:\ADFM\FPGA_DSP_PortLink\FPGA_DSP_PortLink_BiBus_oneFIFO.vwf ;               ;
; Add pins automatically to simulation output waveforms           ; On                                                            ; On            ;
; Check outputs                                                   ; Off                                                           ; Off           ;
; Report simulation coverage                                      ; On                                                            ; On            ;
; Detect setup and hold time violations                           ; Off                                                           ; Off           ;
; Detect glitches                                                 ; Off                                                           ; Off           ;
; Automatically save/load simulation netlist                      ; Off                                                           ; Off           ;
; Disable timing delays in Timing Simulation                      ; Off                                                           ; Off           ;
; Generate Signal Activity File                                   ; Off                                                           ; Off           ;
; Group bus channels in simulation results                        ; Off                                                           ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements ; On                                                            ; On            ;
; Overwrite Waveform Inputs With Simulation Outputs               ; Off                                                           ;               ;
+-----------------------------------------------------------------+---------------------------------------------------------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |FPGA_DSP_PortLink_BiBus_oneFIFO|FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|ALTSYNCRAM ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      13.38 % ;
; Total nodes checked                                 ; 271          ;
; Total output ports checked                          ; 284          ;
; Total output ports with complete 1/0-value coverage ; 38           ;
; Total output ports with no 1/0-value coverage       ; 195          ;
; Total output ports with no 1-value coverage         ; 221          ;
; Total output ports with no 0-value coverage         ; 220          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                                                                             ;
+------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                                      ; Output Port Name                                                                                                                                    ; Output Port Type ;