fpga_dsp_portlink.map.summary

implemention of FPGA and DSP linking port, using Asynchronous mode

Analysis & Synthesis Status : Successful - Thu Jan 03 11:09:21 2008
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : FPGA_DSP_PortLink
Top-level Entity Name : FPGA_DSP_PortLink_BiBus_oneFIFO
Family : Cyclone II
Total combinational functions : 77
Total registers : 103
Total pins : 21
Total virtual pins : 0
Total memory bits : 32,768
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0