fpga_dsp_portlink.map.rpt

implemention of FPGA and DSP linking port, using Asynchronous mode

    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Jan 03 11:09:16 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FPGA_DSP_PortLink -c FPGA_DSP_PortLink
Info: Found 2 design units, including 1 entities, in source file lpm_bustri1.vhd
    Info: Found design unit 1: lpm_bustri1-SYN
    Info: Found entity 1: lpm_bustri1
Info: Found 1 design units, including 1 entities, in source file FPGA_DSP_PortLink_BiBus.bdf
    Info: Found entity 1: FPGA_DSP_PortLink_BiBus
Info: Found 2 design units, including 1 entities, in source file COUT.vhd
    Info: Found design unit 1: cout-SYN
    Info: Found entity 1: COUT
Info: Found 2 design units, including 1 entities, in source file FIFO_WRN_ByDSP.vhd
    Info: Found design unit 1: fifo_wrn_bydsp-SYN
    Info: Found entity 1: FIFO_WRN_ByDSP
Info: Found 2 design units, including 1 entities, in source file Freq_Divider_4.vhd
    Info: Found design unit 1: Freq_Divider_4-ARC
    Info: Found entity 1: Freq_Divider_4
Info: Found 2 design units, including 1 entities, in source file FIFO_RDN_ByDSP.vhd
    Info: Found design unit 1: fifo_rdn_bydsp-SYN
    Info: Found entity 1: FIFO_RDN_ByDSP
Info: Found 1 design units, including 1 entities, in source file FPGA_DSP_PortLink.bdf
    Info: Found entity 1: FPGA_DSP_PortLink
Info: Found 1 design units, including 1 entities, in source file FPGA_DSP_PortLink_Inner.bdf
    Info: Found entity 1: FPGA_DSP_PortLink_Inner
Warning: Entity "MUX" obtained from "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" instead of from Quartus II megafunction library
Info: Found 2 design units, including 1 entities, in source file MUX.vhd
    Info: Found design unit 1: MUX-ARC
    Info: Found entity 1: MUX
Info: Found 1 design units, including 1 entities, in source file fifo_test.bdf
    Info: Found entity 1: fifo_test
Info: Found 2 design units, including 1 entities, in source file en_blk.vhd
    Info: Found design unit 1: en_blk-ARC
    Info: Found entity 1: en_blk
Info: Found 1 design units, including 1 entities, in source file BiPort_Test.bdf
    Info: Found entity 1: BiPort_Test
Info: Found 1 design units, including 1 entities, in source file FPGA_DSP_PortLink_BiBus_oneFIFO.bdf
    Info: Found entity 1: FPGA_DSP_PortLink_BiBus_oneFIFO
Info: Elaborating entity "FPGA_DSP_PortLink_BiBus_oneFIFO" for the top level hierarchy
Info: Elaborating entity "lpm_bustri1" for hierarchy "lpm_bustri1:inst4"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf
    Info: Found entity 1: lpm_bustri
Info: Elaborating entity "lpm_bustri" for hierarchy "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component"
Info: Elaborating entity "en_blk" for hierarchy "en_blk:inst8"
Info: Elaborating entity "MUX" for hierarchy "MUX:inst10"
Info: Elaborating entity "FIFO_RDN_ByDSP" for hierarchy "FIFO_RDN_ByDSP:inst5"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/dcfifo.tdf
    Info: Found entity 1: dcfifo
Info: Elaborating entity "dcfifo" for hierarchy "FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component"
Info: Found 1 design units, including 1 entities, in source file db/dcfifo_fe71.tdf
    Info: Found entity 1: dcfifo_fe71
Info: Elaborating entity "dcfifo_fe71" for hierarchy "FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_p96.tdf
    Info: Found entity 1: a_graycounter_p96
Info: Elaborating entity "a_graycounter_p96" for hierarchy "FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_ik6.tdf
    Info: Found entity 1: a_graycounter_ik6
Info: Elaborating entity "a_graycounter_ik6" for hierarchy "FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ofr.tdf
    Info: Found entity 1: altsyncram_ofr
Info: Elaborating entity "altsyncram_ofr" for hierarchy "FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_uk61.tdf
    Info: Found entity 1: altsyncram_uk61
Info: Elaborating entity "altsyncram_uk61" for hierarchy "FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_hv7.tdf
    Info: Found entity 1: alt_synch_pipe_hv7
Info: Elaborating entity "alt_synch_pipe_hv7" for hierarchy "FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_b09.tdf
    Info: Found entity 1: dffpipe_b09
Info: Elaborating entity "dffpipe_b09" for hierarchy "FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_iv7.tdf
    Info: Found entity 1: alt_synch_pipe_iv7
Info: Elaborating entity "alt_synch_pipe_iv7" for hierarchy "FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_c09.tdf
    Info: Found entity 1: dffpipe_c09
Info: Elaborating entity "dffpipe_c09" for hierarchy "FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8"
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[15]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[14]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[13]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[12]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[11]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[10]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[9]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[8]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[7]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[6]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[5]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[4]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[3]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[2]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[1]" that feeds logic to a wire
    Warning: Converting TRI node "lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component|din[0]" that feeds logic to a wire
Warning: Latch MUX:inst10|O1[15] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[14] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[13] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[12] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[11] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[10] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[9] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[8] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Warning: Latch MUX:inst10|O1[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal CS
Info: Implemented 192 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 0 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 155 logic cells
    Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 50 warnings
    Info: Processing ended: Thu Jan 03 11:09:21 2008
    Info: Elapsed time: 00:00:06