fpga_dsp_portlink.map.rpt

implemention of FPGA and DSP linking port, using Asynchronous mode

; Assignment                      ; Value ; from ; to                 ;
+---------------------------------+-------+------+--------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                  ;
+---------------------------------+-------+------+--------------------+


+------------------------------------------------------------------------------------------------+
; Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated ;
+---------------------------------+-------+-----------------+------------------------------------+
; Assignment                      ; Value ; from            ; to                                 ;
+---------------------------------+-------+-----------------+------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -               ; -                                  ;
; SUPPRESS_DA_RULE_INTERNAL       ; d101  ; -               ; -                                  ;
; POWER_UP_LEVEL                  ; LOW   ; -               ; p0addr                             ;
; POWER_UP_LEVEL                  ; LOW   ; -               ; rdaclr                             ;
; CUT                             ; ON    ; rdptr_g         ; ws_dgrp|dffpipe8|dffe9a            ;
; CUT                             ; ON    ; delayed_wrptr_g ; rs_dgwp|dffpipe5|dffe6a            ;
+---------------------------------+-------+-----------------+------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3 ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; from ; to                                                                                   ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                    ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp ;
+-----------------------+-------+------+------------------------------------------------------------------------------------+
; Assignment            ; Value ; from ; to                                                                                 ;
+-----------------------+-------+------+------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                  ;
+-----------------------+-------+------+------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; from ; to                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp ;
+-----------------------+-------+------+------------------------------------------------------------------------------------+
; Assignment            ; Value ; from ; to                                                                                 ;
+-----------------------+-------+------+------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF   ; -    ; -                                                                                  ;
+-----------------------+-------+------+------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8 ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; from ; to                                                                                            ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                             ;
+---------------------------------+-------+------+-----------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component ;
+----------------+-------+-----------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                  ;
+----------------+-------+-----------------------------------------------------------------------+
; LPM_WIDTH      ; 16    ; Integer                                                               ;
+----------------+-------+-----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component ;
+-------------------------+-------------+---------------------------------------------------+
; Parameter Name          ; Value       ; Type                                              ;
+-------------------------+-------------+---------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                        ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                      ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                      ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                    ;
; LPM_WIDTH               ; 16          ; Integer                                           ;
; LPM_NUMWORDS            ; 2048        ; Integer                                           ;
; LPM_WIDTHU              ; 11          ; Integer                                           ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                           ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                           ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                           ;
; USE_EAB                 ; ON          ; Untyped                                           ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                           ;
; DELAY_RDUSEDW           ; 1           ; Untyped                                           ;
; DELAY_WRUSEDW           ; 1           ; Untyped                                           ;
; RDSYNC_DELAYPIPE        ; 4           ; Integer                                           ;
; WRSYNC_DELAYPIPE        ; 4           ; Integer                                           ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                           ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                           ;
; CBXI_PARAMETER          ; dcfifo_fe71 ; Untyped                                           ;
+-------------------------+-------------+---------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------+
; dcfifo Parameter Settings by Entity Instance                              ;
+----------------------------+----------------------------------------------+
; Name                       ; Value                                        ;
+----------------------------+----------------------------------------------+
; Number of entity instances ; 1                                            ;
; Entity Instance            ; FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component ;
;     -- FIFO Type           ; Dual Clock                                   ;
;     -- LPM_WIDTH           ; 16                                           ;
;     -- LPM_NUMWORDS        ; 2048                                         ;
;     -- LPM_SHOWAHEAD       ; OFF                                          ;
;     -- USE_EAB             ; ON                                           ;
+----------------------------+----------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis