fpga_dsp_portlink.tan.qmsg

implemention of FPGA and DSP linking port, using Asynchronous mode

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off FPGA_DSP_PortLink -c FPGA_DSP_PortLink --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FPGA_DSP_PortLink -c FPGA_DSP_PortLink --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[11\] " "Warning: Node \"MUX:inst10\|O1\[11\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[15\] " "Warning: Node \"MUX:inst10\|O1\[15\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[8\] " "Warning: Node \"MUX:inst10\|O1\[8\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[14\] " "Warning: Node \"MUX:inst10\|O1\[14\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[2\] " "Warning: Node \"MUX:inst10\|O1\[2\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[13\] " "Warning: Node \"MUX:inst10\|O1\[13\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[5\] " "Warning: Node \"MUX:inst10\|O1\[5\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[12\] " "Warning: Node \"MUX:inst10\|O1\[12\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[4\] " "Warning: Node \"MUX:inst10\|O1\[4\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[10\] " "Warning: Node \"MUX:inst10\|O1\[10\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[3\] " "Warning: Node \"MUX:inst10\|O1\[3\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[9\] " "Warning: Node \"MUX:inst10\|O1\[9\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[6\] " "Warning: Node \"MUX:inst10\|O1\[6\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[7\] " "Warning: Node \"MUX:inst10\|O1\[7\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[0\] " "Warning: Node \"MUX:inst10\|O1\[0\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "MUX:inst10\|O1\[1\] " "Warning: Node \"MUX:inst10\|O1\[1\]\" is a latch" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}