a_graycounter_986.tdf

implemention of FPGA and DSP linking port, using Asynchronous mode

--a_graycounter DEVICE_FAMILY="Cyclone II" WIDTH=2 aclr clock cnt_en q
--VERSION_BEGIN 5.1 cbx_a_gray2bin 2005:04:27:12:26:10:SJ cbx_a_graycounter 2005:07:27:11:56:48:SJ cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_flex10ke 2002:10:19:11:54:38:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ  VERSION_END


--  Copyright (C) 1991-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = reg 2 
SUBDESIGN a_graycounter_986
( 
	aclr	:	input;
	clock	:	input;
	cnt_en	:	input;
	q[1..0]	:	output;
) 
VARIABLE 
	dffe3a[1..0] : dffe;
	power_modified_counter_values[1..0]	: WIRE;
	updown	: NODE;

BEGIN 
	dffe3a[].CLK = clock;
	dffe3a[].CLRN = (! aclr);
	dffe3a[].D = ( ((cnt_en & (updown $ (! power_modified_counter_values[0..0]))) # ((! cnt_en) & power_modified_counter_values[1..1])), ((cnt_en & (updown $ power_modified_counter_values[1..1])) # ((! cnt_en) & power_modified_counter_values[0..0])));
	power_modified_counter_values[] = ( dffe3a[1..0].Q);
	q[] = power_modified_counter_values[];
	updown = VCC;
END;
--VALID FILE