dffpipe_0v8.tdf

implemention of FPGA and DSP linking port, using Asynchronous mode

--dffpipe DELAY=2 WIDTH=2 clock d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 5.1 cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratixii 2005:07:27:05:50:56:SJ cbx_util_mgl 2005:09:13:05:23:22:SJ  VERSION_END


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--synthesis_resources = reg 4 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_0v8
( 
	clock	:	input;
	d[1..0]	:	input;
	q[1..0]	:	output;
) 
VARIABLE 
	dffe14a[1..0] : dffe;
	dffe15a[1..0] : dffe;
	clrn	: NODE;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe14a[].CLK = clock;
	dffe14a[].CLRN = clrn;
	dffe14a[].D = (d[] & (! sclr));
	dffe14a[].ENA = ena;
	dffe14a[].PRN = prn;
	dffe15a[].CLK = clock;
	dffe15a[].CLRN = clrn;
	dffe15a[].D = (dffe14a[].Q & (! sclr));
	dffe15a[].ENA = ena;
	dffe15a[].PRN = prn;
	clrn = VCC;
	ena = VCC;
	prn = VCC;
	q[] = dffe15a[].Q;
	sclr = GND;
END;
--VALID FILE