altsyncram_ofr.tdf

implemention of FPGA and DSP linking port, using Asynchronous mode

--altsyncram ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" DEVICE_FAMILY="Cyclone II" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="CLOCK1" RAM_BLOCK_TYPE="M4K" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b addressstall_b clock0 clock1 clocken1 data_a q_b wren_a
--VERSION_BEGIN 5.1 cbx_altsyncram 2005:10:21:05:19:54:SJ cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_lpm_compare 2005:07:12:04:41:28:SJ cbx_lpm_decode 2005:04:28:09:28:48:SJ cbx_lpm_mux 2005:04:28:09:25:00:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ cbx_util_mgl 2005:09:13:05:23:22:SJ  VERSION_END


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FUNCTION altsyncram_uk61 (address_a[10..0], address_b[10..0], addressstall_a, clock0, clock1, clocken0, data_a[15..0], data_b[15..0], wren_a, wren_b)
RETURNS ( q_a[15..0], q_b[15..0]);

--synthesis_resources = M4K 8 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_ofr
( 
	address_a[10..0]	:	input;
	address_b[10..0]	:	input;
	addressstall_b	:	input;
	clock0	:	input;
	clock1	:	input;
	clocken1	:	input;
	data_a[15..0]	:	input;
	q_b[15..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	altsyncram3 : altsyncram_uk61;

BEGIN 
	altsyncram3.address_a[] = address_b[];
	altsyncram3.address_b[] = address_a[];
	altsyncram3.addressstall_a = addressstall_b;
	altsyncram3.clock0 = clock1;
	altsyncram3.clock1 = clock0;
	altsyncram3.clocken0 = clocken1;
	altsyncram3.data_a[] = B"1111111111111111";
	altsyncram3.data_b[] = data_a[];
	altsyncram3.wren_a = B"0";
	altsyncram3.wren_b = wren_a;
	q_b[] = altsyncram3.q_a[];
END;
--VALID FILE