fpga_dsp_portlink.map.qmsg

implemention of FPGA and DSP linking port, using Asynchronous mode

{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[15\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[15\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[14\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[14\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[13\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[13\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[12\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[12\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[11\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[11\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[10\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[10\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[9\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[9\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[8\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[8\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[7\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[7\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[6\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[6\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[5\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[5\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[4\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[4\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[3\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[3\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[2\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[2\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[1\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[1\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[0\] " "Warning: Converting TRI node \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\|din\[0\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 44 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[15\] " "Warning: Latch MUX:inst10\|O1\[15\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[14\] " "Warning: Latch MUX:inst10\|O1\[14\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[13\] " "Warning: Latch MUX:inst10\|O1\[13\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[12\] " "Warning: Latch MUX:inst10\|O1\[12\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[11\] " "Warning: Latch MUX:inst10\|O1\[11\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[10\] " "Warning: Latch MUX:inst10\|O1\[10\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[9\] " "Warning: Latch MUX:inst10\|O1\[9\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[8\] " "Warning: Latch MUX:inst10\|O1\[8\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[7\] " "Warning: Latch MUX:inst10\|O1\[7\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[6\] " "Warning: Latch MUX:inst10\|O1\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[5\] " "Warning: Latch MUX:inst10\|O1\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[4\] " "Warning: Latch MUX:inst10\|O1\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[3\] " "Warning: Latch MUX:inst10\|O1\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[2\] " "Warning: Latch MUX:inst10\|O1\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[1\] " "Warning: Latch MUX:inst10\|O1\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "MUX:inst10\|O1\[0\] " "Warning: Latch MUX:inst10\|O1\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA CS " "Warning: Ports D and ENA on the latch are fed by the same signal CS" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 208 -72 96 224 "CS" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 18 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "192 " "Info: Implemented 192 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "0 " "Info: Implemented 0 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "155 " "Info: Implemented 155 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 50 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 50 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 03 11:09:21 2008 " "Info: Processing ended: Thu Jan 03 11:09:21 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}