fpga_dsp_portlink.map.qmsg

implemention of FPGA and DSP linking port, using Asynchronous mode

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MUX MUX:inst10 " "Info: Elaborating entity \"MUX\" for hierarchy \"MUX:inst10\"" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "inst10" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 56 688 840 184 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FIFO_RDN_ByDSP FIFO_RDN_ByDSP:inst5 " "Info: Elaborating entity \"FIFO_RDN_ByDSP\" for hierarchy \"FIFO_RDN_ByDSP:inst5\"" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "inst5" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 216 352 512 384 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus51/libraries/megafunctions/dcfifo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/dcfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo " "Info: Found entity 1: dcfifo" {  } { { "dcfifo.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/dcfifo.tdf" 106 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component " "Info: Elaborating entity \"dcfifo\" for hierarchy \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\"" {  } { { "FIFO_RDN_ByDSP.vhd" "dcfifo_component" { Text "E:/ADFM/FPGA_DSP_PortLink/FIFO_RDN_ByDSP.vhd" 94 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dcfifo_fe71.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dcfifo_fe71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo_fe71 " "Info: Found entity 1: dcfifo_fe71" {  } { { "db/dcfifo_fe71.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 34 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo_fe71 FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated " "Info: Elaborating entity \"dcfifo_fe71\" for hierarchy \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\"" {  } { { "dcfifo.tdf" "auto_generated" { Text "d:/program files/altera/quartus51/libraries/megafunctions/dcfifo.tdf" 185 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_p96.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_p96.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_p96 " "Info: Found entity 1: a_graycounter_p96" {  } { { "db/a_graycounter_p96.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_p96.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_p96 FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p " "Info: Elaborating entity \"a_graycounter_p96\" for hierarchy \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_p96:rdptr_g1p\"" {  } { { "db/dcfifo_fe71.tdf" "rdptr_g1p" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 46 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_ik6.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_ik6.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_ik6 " "Info: Found entity 1: a_graycounter_ik6" {  } { { "db/a_graycounter_ik6.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/a_graycounter_ik6.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_ik6 FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p " "Info: Elaborating entity \"a_graycounter_ik6\" for hierarchy \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|a_graycounter_ik6:wrptr_g1p\"" {  } { { "db/dcfifo_fe71.tdf" "wrptr_g1p" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 47 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ofr.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ofr.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ofr " "Info: Found entity 1: altsyncram_ofr" {  } { { "db/altsyncram_ofr.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/altsyncram_ofr.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ofr FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|altsyncram_ofr:fifo_ram " "Info: Elaborating entity \"altsyncram_ofr\" for hierarchy \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|altsyncram_ofr:fifo_ram\"" {  } { { "db/dcfifo_fe71.tdf" "fifo_ram" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 48 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_uk61.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_uk61.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_uk61 " "Info: Found entity 1: altsyncram_uk61" {  } { { "db/altsyncram_uk61.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/altsyncram_uk61.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_uk61 FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|altsyncram_ofr:fifo_ram\|altsyncram_uk61:altsyncram3 " "Info: Elaborating entity \"altsyncram_uk61\" for hierarchy \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|altsyncram_ofr:fifo_ram\|altsyncram_uk61:altsyncram3\"" {  } { { "db/altsyncram_ofr.tdf" "altsyncram3" { Text "E:/ADFM/FPGA_DSP_PortLink/db/altsyncram_ofr.tdf" 39 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_hv7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_hv7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_hv7 " "Info: Found entity 1: alt_synch_pipe_hv7" {  } { { "db/alt_synch_pipe_hv7.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/alt_synch_pipe_hv7.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_hv7 FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_hv7:rs_dgwp " "Info: Elaborating entity \"alt_synch_pipe_hv7\" for hierarchy \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_hv7:rs_dgwp\"" {  } { { "db/dcfifo_fe71.tdf" "rs_dgwp" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 60 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_b09.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_b09.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_b09 " "Info: Found entity 1: dffpipe_b09" {  } { { "db/dffpipe_b09.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dffpipe_b09.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_b09 FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_hv7:rs_dgwp\|dffpipe_b09:dffpipe5 " "Info: Elaborating entity \"dffpipe_b09\" for hierarchy \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_hv7:rs_dgwp\|dffpipe_b09:dffpipe5\"" {  } { { "db/alt_synch_pipe_hv7.tdf" "dffpipe5" { Text "E:/ADFM/FPGA_DSP_PortLink/db/alt_synch_pipe_hv7.tdf" 33 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_iv7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_iv7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_iv7 " "Info: Found entity 1: alt_synch_pipe_iv7" {  } { { "db/alt_synch_pipe_iv7.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/alt_synch_pipe_iv7.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_iv7 FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_iv7:ws_dgrp " "Info: Elaborating entity \"alt_synch_pipe_iv7\" for hierarchy \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_iv7:ws_dgrp\"" {  } { { "db/dcfifo_fe71.tdf" "ws_dgrp" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dcfifo_fe71.tdf" 61 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_c09.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_c09.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_c09 " "Info: Found entity 1: dffpipe_c09" {  } { { "db/dffpipe_c09.tdf" "" { Text "E:/ADFM/FPGA_DSP_PortLink/db/dffpipe_c09.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_c09 FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_iv7:ws_dgrp\|dffpipe_c09:dffpipe8 " "Info: Elaborating entity \"dffpipe_c09\" for hierarchy \"FIFO_RDN_ByDSP:inst5\|dcfifo:dcfifo_component\|dcfifo_fe71:auto_generated\|alt_synch_pipe_iv7:ws_dgrp\|dffpipe_c09:dffpipe8\"" {  } { { "db/alt_synch_pipe_iv7.tdf" "dffpipe8" { Text "E:/ADFM/FPGA_DSP_PortLink/db/alt_synch_pipe_iv7.tdf" 33 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}