fifo_rdn_bydsp_inst.vhd

来自「implemention of FPGA and DSP linking por」· VHDL 代码 · 共 11 行

FIFO_RDN_ByDSP_inst : FIFO_RDN_ByDSP PORT MAP (
		data	 => data_sig,
		rdclk	 => rdclk_sig,
		rdreq	 => rdreq_sig,
		wrclk	 => wrclk_sig,
		wrreq	 => wrreq_sig,
		q	 => q_sig,
		rdempty	 => rdempty_sig,
		wrfull	 => wrfull_sig
	);