fpga_dsp_portlink.fit.summary

来自「implemention of FPGA and DSP linking por」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Thu Jan 03 11:09:32 2008
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : FPGA_DSP_PortLink
Top-level Entity Name : FPGA_DSP_PortLink_BiBus_oneFIFO
Family : Cyclone II
Device : EP2C8Q208C7
Timing Models : Preliminary
Total logic elements : 143 / 8,256 ( 2 % )
Total registers : 103
Total pins : 21 / 138 ( 15 % )
Total virtual pins : 0
Total memory bits : 32,768 / 165,888 ( 20 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )