fpga_dsp_portlink.fit.rpt

implemention of FPGA and DSP linking port, using Asynchronous mode

; Auto Global Memory Control Signals                   ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/Cyclone II       ; Auto                           ; Auto                           ;
; Auto Delay Chains                                    ; On                             ; On                             ;
; Auto Merge PLLs                                      ; On                             ; On                             ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; On                       ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve nCEO pin after configuration         ; As output driving ground ;
; Reserve ASDO pin after configuration.        ; As input tri-stated      ;
; Reserve all unused pins                      ; As input tri-stated      ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.pin.


+-------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                           ;
+---------------------------------------------+---------------------------+
; Resource                                    ; Usage                     ;
+---------------------------------------------+---------------------------+
; Total logic elements                        ; 143 / 8,256 ( 2 % )       ;
;     -- Combinational with no register       ; 40                        ;
;     -- Register only                        ; 64                        ;
;     -- Combinational with a register        ; 39                        ;
;                                             ;                           ;
; Logic element usage by number of LUT inputs ;                           ;
;     -- 4 input functions                    ; 17                        ;
;     -- 3 input functions                    ; 55                        ;
;     -- <=2 input functions                  ; 7                         ;
;     -- Register only                        ; 64                        ;
;         -- Combinational cells for routing  ; 41                        ;
;                                             ;                           ;
; Logic elements by mode                      ;                           ;
;     -- normal mode                          ; 57                        ;
;     -- arithmetic mode                      ; 22                        ;
;                                             ;                           ;
; Total registers                             ; 103 / 8,256 ( 1 % )       ;
; Total LABs                                  ; 21 / 516 ( 4 % )          ;
; User inserted logic elements                ; 0                         ;
; Virtual pins                                ; 0                         ;
; I/O pins                                    ; 21 / 138 ( 15 % )         ;
;     -- Clock pins                           ; 0 / 4 ( 0 % )             ;
; Global signals                              ; 2                         ;
; M4Ks                                        ; 8 / 36 ( 22 % )           ;
; Total memory bits                           ; 32,768 / 165,888 ( 20 % ) ;
; Total RAM block bits                        ; 36,864 / 165,888 ( 22 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 36 ( 0 % )            ;
; PLLs                                        ; 0 / 2 ( 0 % )             ;
; Global clocks                               ; 2 / 8 ( 25 % )            ;
; Maximum fan-out node                        ; WE                        ;
; Maximum fan-out                             ; 64                        ;
; Highest non-global fan-out signal           ; WE                        ;
; Highest non-global fan-out                  ; 64                        ;
; Total fan-out                               ; 788                       ;
; Average fan-out                             ; 3.05                      ;
+---------------------------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                    ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Addr[0] ; 144   ; 3        ; 34           ; 13           ; 0           ; 18                    ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVCMOS       ; Off         ; User                 ;
; Addr[1] ; 143   ; 3        ; 34           ; 13           ; 1           ; 5                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVCMOS       ; Off         ; User                 ;
; CS      ; 115   ; 3        ; 34           ; 4            ; 0           ; 19                    ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVCMOS       ; Off         ; User                 ;
; RE      ; 116   ; 3        ; 34           ; 5            ; 1           ; 55                    ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVCMOS       ; Off         ; User                 ;
; WE      ; 118   ; 3        ; 34           ; 7            ; 1           ; 64                    ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVCMOS       ; Off         ; User                 ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Bidir Pins                                                                                                                                                                                                                                                                                                                                         ;