pll0_waveforms.html

来自「implemention of FPGA and DSP linking por」· HTML 代码 · 共 14 行

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<title>Sample Waveforms for PLL0.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file PLL0.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design PLL0.vhd. The design PLL0.vhd has Cyclone II FAST pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 8421 ps. Input port PLLENA is used. This port is active high. When deasserted, it will cause the PLL to unlock, and the LOCKED port and all CLK outputs will drop to zero. </P>
<CENTER><img src=PLL0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
<P><FONT size=3></P>
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pll0_waveforms.html - 源码说明

本页面展示了「implemention of FPGA and DSP linking port, using Asynchronous mode」中的 pll0_waveforms.html 源码文件，采用 HTML 编程语言编写，共 14 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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