fpga_dsp_portlink.tan.rpt

implemention of FPGA and DSP linking port, using Asynchronous mode

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                       ;
+------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                 ; To                                                                                                                                                    ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 9.077 ns                         ; Addr[0]                                                                                                                              ; FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10]                 ; --         ; RE       ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 10.407 ns                        ; MUX:inst10|O1[0]                                                                                                                     ; TO_DSP[0]                                                                                                                                             ; Addr[0]    ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 7.722 ns                         ; Addr[0]                                                                                                                              ; TO_DSP[4]                                                                                                                                             ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -1.869 ns                        ; CS                                                                                                                                   ; MUX:inst10|O1[2]                                                                                                                                      ; --         ; Addr[0]  ; 0            ;
; Clock Setup: 'WE'            ; N/A   ; None          ; 132.59 MHz ( period = 7.542 ns ) ; FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[9] ; FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|ram_block4a3~portb_we_reg ; WE         ; WE       ; 0            ;
; Clock Setup: 'RE'            ; N/A   ; None          ; 156.05 MHz ( period = 6.408 ns ) ; FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10]   ; FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_p96:rdptr_g1p|power_modified_counter_values[10]                 ; RE         ; RE       ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                                                      ;                                                                                                                                                       ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                             ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+
; Option                                                ; Setting            ; From            ; To                      ; Entity Name ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+
; Device Name                                           ; EP2C8Q208C7        ;                 ;                         ;             ;
; Timing Models                                         ; Preliminary        ;                 ;                         ;             ;
; Number of source nodes to report per destination node ; 10                 ;                 ;                         ;             ;
; Number of destination nodes to report                 ; 10                 ;                 ;                         ;             ;
; Number of paths to report                             ; 200                ;                 ;                         ;             ;
; Report Minimum Timing Checks                          ; Off                ;                 ;                         ;             ;
; Use Fast Timing Models                                ; Off                ;                 ;                         ;             ;
; Report IO Paths Separately                            ; Off                ;                 ;                         ;             ;
; Default hold multicycle                               ; Same As Multicycle ;                 ;                         ;             ;
; Cut paths between unrelated clock domains             ; On                 ;                 ;                         ;             ;
; Cut off read during write signal paths                ; On                 ;                 ;                         ;             ;
; Cut off feedback from I/O pins                        ; On                 ;                 ;                         ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;                 ;                         ;             ;
; Ignore Clock Settings                                 ; Off                ;                 ;                         ;             ;
; Analyze latches as synchronous elements               ; On                 ;                 ;                         ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;                 ;                         ;             ;
; Enable Clock Latency                                  ; Off                ;                 ;                         ;             ;
; Cut Timing Path                                       ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe5|dffe6a ; dcfifo_fe71 ;
; Cut Timing Path                                       ; On                 ; rdptr_g         ; ws_dgrp|dffpipe8|dffe9a ; dcfifo_fe71 ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+