fpga_dsp_portlink.tan.rpt

implemention of FPGA and DSP linking port, using Asynchronous mode

Timing Analyzer report for FPGA_DSP_PortLink
Thu Jan 03 11:09:39 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'RE'
  6. Clock Setup: 'WE'
  7. tsu
  8. tco
  9. tpd
 10. th
 11. Timing Analyzer Messages



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; Legal Notice ;
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Copyright (C) 1991-2005 Altera Corporation
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and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
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to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.