fpga_dsp_portlink.fit.eqn

implemention of FPGA and DSP linking port, using Asynchronous mode

--E1L33 is MUX:inst10|O1~525 at LCCOMB_X22_Y5_N26
E1L33 = E1L32 & H1L57 & (!Addr[1]) # !E1L32 & (P1_q_a[1]);


--P1_q_a[0] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[0] at M4K_X11_Y8
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_a[0]_PORT_A_data_in_reg = DFFE(P1_q_a[0]_PORT_A_data_in, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[0]_PORT_B_data_in = BUS(A1L38, A1L37);
P1_q_a[0]_PORT_B_data_in_reg = DFFE(P1_q_a[0]_PORT_B_data_in, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[0]_PORT_A_address_reg = DFFE(P1_q_a[0]_PORT_A_address, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[0]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[0]_PORT_B_address_reg = DFFE(P1_q_a[0]_PORT_B_address, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_write_enable = GND;
P1_q_a[0]_PORT_A_write_enable_reg = DFFE(P1_q_a[0]_PORT_A_write_enable, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[0]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[0]_PORT_B_write_enable_reg = DFFE(P1_q_a[0]_PORT_B_write_enable, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_clock_0 = !RE;
P1_q_a[0]_clock_1 = !WE;
P1_q_a[0]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[0]_PORT_A_data_out = MEMORY(P1_q_a[0]_PORT_A_data_in_reg, P1_q_a[0]_PORT_B_data_in_reg, P1_q_a[0]_PORT_A_address_reg, P1_q_a[0]_PORT_B_address_reg, P1_q_a[0]_PORT_A_write_enable_reg, P1_q_a[0]_PORT_B_write_enable_reg, , , P1_q_a[0]_clock_0, P1_q_a[0]_clock_1, P1_q_a[0]_clock_enable_0, , , );
P1_q_a[0]_PORT_A_data_out_reg = DFFE(P1_q_a[0]_PORT_A_data_out, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[0] = P1_q_a[0]_PORT_A_data_out_reg[0];

--P1_q_a[1] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[1] at M4K_X11_Y8
P1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_a[0]_PORT_A_data_in_reg = DFFE(P1_q_a[0]_PORT_A_data_in, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[0]_PORT_B_data_in = BUS(A1L38, A1L37);
P1_q_a[0]_PORT_B_data_in_reg = DFFE(P1_q_a[0]_PORT_B_data_in, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[0]_PORT_A_address_reg = DFFE(P1_q_a[0]_PORT_A_address, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[0]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[0]_PORT_B_address_reg = DFFE(P1_q_a[0]_PORT_B_address, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_PORT_A_write_enable = GND;
P1_q_a[0]_PORT_A_write_enable_reg = DFFE(P1_q_a[0]_PORT_A_write_enable, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[0]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[0]_PORT_B_write_enable_reg = DFFE(P1_q_a[0]_PORT_B_write_enable, P1_q_a[0]_clock_1, , , );
P1_q_a[0]_clock_0 = !RE;
P1_q_a[0]_clock_1 = !WE;
P1_q_a[0]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[0]_PORT_A_data_out = MEMORY(P1_q_a[0]_PORT_A_data_in_reg, P1_q_a[0]_PORT_B_data_in_reg, P1_q_a[0]_PORT_A_address_reg, P1_q_a[0]_PORT_B_address_reg, P1_q_a[0]_PORT_A_write_enable_reg, P1_q_a[0]_PORT_B_write_enable_reg, , , P1_q_a[0]_clock_0, P1_q_a[0]_clock_1, P1_q_a[0]_clock_enable_0, , , );
P1_q_a[0]_PORT_A_data_out_reg = DFFE(P1_q_a[0]_PORT_A_data_out, P1_q_a[0]_clock_0, , , P1_q_a[0]_clock_enable_0);
P1_q_a[1] = P1_q_a[0]_PORT_A_data_out_reg[1];


--H1_rdptr_g[2] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[2] at LCFF_X21_Y8_N29
H1_rdptr_g[2] = DFFEAS(H1L39, !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--H1_rdptr_g[4] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[4] at LCFF_X21_Y8_N31
H1_rdptr_g[4] = DFFEAS(H1L43, !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--Q1_dffe7a[4] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[4] at LCFF_X22_Y8_N25
Q1_dffe7a[4] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  ,  , Q1_dffe6a[4],  ,  , VCC);


--Q1_dffe7a[2] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[2] at LCFF_X22_Y8_N29
Q1_dffe7a[2] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  ,  , Q1_dffe6a[2],  ,  , VCC);


--H1L28 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~71 at LCCOMB_X22_Y8_N28
H1L28 = H1_rdptr_g[4] & Q1_dffe7a[4] & (Q1_dffe7a[2] $ !H1_rdptr_g[2]) # !H1_rdptr_g[4] & !Q1_dffe7a[4] & (Q1_dffe7a[2] $ !H1_rdptr_g[2]);


--H1_rdptr_g[8] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[8] at LCFF_X23_Y8_N1
H1_rdptr_g[8] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  , H1_valid_rdreq, K1_power_modified_counter_values[8],  ,  , VCC);


--H1_rdptr_g[10] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[10] at LCFF_X23_Y8_N3
H1_rdptr_g[10] = DFFEAS(H1L53, !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--Q1_dffe7a[10] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[10] at LCFF_X22_Y8_N9
Q1_dffe7a[10] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  ,  , Q1_dffe6a[10],  ,  , VCC);


--Q1_dffe7a[8] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[8] at LCFF_X22_Y8_N13
Q1_dffe7a[8] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  ,  , Q1_dffe6a[8],  ,  , VCC);


--H1L29 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~72 at LCCOMB_X22_Y8_N12
H1L29 = Q1_dffe7a[10] & H1_rdptr_g[10] & (H1_rdptr_g[8] $ !Q1_dffe7a[8]) # !Q1_dffe7a[10] & !H1_rdptr_g[10] & (H1_rdptr_g[8] $ !Q1_dffe7a[8]);


--H1_rdptr_g[9] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[9] at LCFF_X23_Y8_N31
H1_rdptr_g[9] = DFFEAS(H1L51, !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--H1_rdptr_g[0] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[0] at LCFF_X21_Y8_N3
H1_rdptr_g[0] = DFFEAS(H1L36, !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--Q1_dffe7a[0] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[0] at LCFF_X22_Y8_N7
Q1_dffe7a[0] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  ,  , Q1_dffe6a[0],  ,  , VCC);


--Q1_dffe7a[9] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[9] at LCFF_X22_Y8_N5
Q1_dffe7a[9] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  ,  , Q1_dffe6a[9],  ,  , VCC);


--H1L30 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~73 at LCCOMB_X22_Y8_N4
H1L30 = H1_rdptr_g[0] & Q1_dffe7a[0] & (H1_rdptr_g[9] $ !Q1_dffe7a[9]) # !H1_rdptr_g[0] & !Q1_dffe7a[0] & (H1_rdptr_g[9] $ !Q1_dffe7a[9]);


--H1_rdptr_g[6] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[6] at LCFF_X21_Y8_N15
H1_rdptr_g[6] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  , H1_valid_rdreq, K1_power_modified_counter_values[6],  ,  , VCC);


--H1_rdptr_g[7] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[7] at LCFF_X21_Y8_N23
H1_rdptr_g[7] = DFFEAS(H1L48, !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--Q1_dffe7a[7] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[7] at LCFF_X22_Y8_N1
Q1_dffe7a[7] = DFFEAS(Q1L28, !RE,  ,  ,  ,  ,  ,  ,  );


--Q1_dffe7a[6] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[6] at LCFF_X22_Y8_N19
Q1_dffe7a[6] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  ,  , Q1_dffe6a[6],  ,  , VCC);


--H1L31 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~74 at LCCOMB_X22_Y8_N18
H1L31 = H1_rdptr_g[7] & Q1_dffe7a[7] & (Q1_dffe7a[6] $ !H1_rdptr_g[6]) # !H1_rdptr_g[7] & !Q1_dffe7a[7] & (Q1_dffe7a[6] $ !H1_rdptr_g[6]);


--H1L32 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~75 at LCCOMB_X22_Y8_N26
H1L32 = H1L29 & H1L28 & H1L30 & H1L31;


--H1_rdptr_g[3] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[3] at LCFF_X21_Y8_N11
H1_rdptr_g[3] = DFFEAS(H1L41, !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--H1_rdptr_g[1] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[1] at LCFF_X21_Y8_N27
H1_rdptr_g[1] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  , H1_valid_rdreq, K1_power_modified_counter_values[1],  ,  , VCC);


--Q1_dffe7a[1] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[1] at LCFF_X22_Y8_N11
Q1_dffe7a[1] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  ,  , Q1_dffe6a[1],  ,  , VCC);


--Q1_dffe7a[3] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[3] at LCFF_X22_Y7_N17
Q1_dffe7a[3] = DFFEAS(Q1L23, !RE,  ,  ,  ,  ,  ,  ,  );


--H1L33 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~76 at LCCOMB_X22_Y8_N10
H1L33 = H1_rdptr_g[3] & Q1_dffe7a[3] & (Q1_dffe7a[1] $ !H1_rdptr_g[1]) # !H1_rdptr_g[3] & !Q1_dffe7a[3] & (Q1_dffe7a[1] $ !H1_rdptr_g[1]);


--H1_rdptr_g[5] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdptr_g[5] at LCFF_X21_Y8_N19
H1_rdptr_g[5] = DFFEAS(H1L45, !RE,  ,  , H1_valid_rdreq,  ,  ,  ,  );


--Q1_dffe7a[5] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5|dffe7a[5] at LCFF_X22_Y8_N15
Q1_dffe7a[5] = DFFEAS(UNCONNECTED_DATAIN, !RE,  ,  ,  , Q1_dffe6a[5],  ,  , VCC);


--H1L27 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|rdempty_eq_comp_aeb_int~0 at LCCOMB_X22_Y8_N14
H1L27 = H1L33 & H1L32 & (Q1_dffe7a[5] $ !H1_rdptr_g[5]);


--E1L34 is MUX:inst10|O1~526 at LCCOMB_X22_Y5_N12
E1L34 = E1L32 & !Addr[1] & (H1L27) # !E1L32 & (P1_q_a[0]);