fpga_dsp_portlink.fit.eqn

implemention of FPGA and DSP linking port, using Asynchronous mode

--P1_q_a[2] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[2] at M4K_X11_Y5
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[2]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_a[2]_PORT_A_data_in_reg = DFFE(P1_q_a[2]_PORT_A_data_in, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[2]_PORT_B_data_in = BUS(A1L36, A1L25);
P1_q_a[2]_PORT_B_data_in_reg = DFFE(P1_q_a[2]_PORT_B_data_in, P1_q_a[2]_clock_1, , , );
P1_q_a[2]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[2]_PORT_A_address_reg = DFFE(P1_q_a[2]_PORT_A_address, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[2]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[2]_PORT_B_address_reg = DFFE(P1_q_a[2]_PORT_B_address, P1_q_a[2]_clock_1, , , );
P1_q_a[2]_PORT_A_write_enable = GND;
P1_q_a[2]_PORT_A_write_enable_reg = DFFE(P1_q_a[2]_PORT_A_write_enable, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[2]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[2]_PORT_B_write_enable_reg = DFFE(P1_q_a[2]_PORT_B_write_enable, P1_q_a[2]_clock_1, , , );
P1_q_a[2]_clock_0 = !RE;
P1_q_a[2]_clock_1 = !WE;
P1_q_a[2]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[2]_PORT_A_data_out = MEMORY(P1_q_a[2]_PORT_A_data_in_reg, P1_q_a[2]_PORT_B_data_in_reg, P1_q_a[2]_PORT_A_address_reg, P1_q_a[2]_PORT_B_address_reg, P1_q_a[2]_PORT_A_write_enable_reg, P1_q_a[2]_PORT_B_write_enable_reg, , , P1_q_a[2]_clock_0, P1_q_a[2]_clock_1, P1_q_a[2]_clock_enable_0, , , );
P1_q_a[2]_PORT_A_data_out_reg = DFFE(P1_q_a[2]_PORT_A_data_out, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[2] = P1_q_a[2]_PORT_A_data_out_reg[0];

--P1_q_a[13] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[13] at M4K_X11_Y5
P1_q_a[2]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_a[2]_PORT_A_data_in_reg = DFFE(P1_q_a[2]_PORT_A_data_in, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[2]_PORT_B_data_in = BUS(A1L36, A1L25);
P1_q_a[2]_PORT_B_data_in_reg = DFFE(P1_q_a[2]_PORT_B_data_in, P1_q_a[2]_clock_1, , , );
P1_q_a[2]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[2]_PORT_A_address_reg = DFFE(P1_q_a[2]_PORT_A_address, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[2]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[2]_PORT_B_address_reg = DFFE(P1_q_a[2]_PORT_B_address, P1_q_a[2]_clock_1, , , );
P1_q_a[2]_PORT_A_write_enable = GND;
P1_q_a[2]_PORT_A_write_enable_reg = DFFE(P1_q_a[2]_PORT_A_write_enable, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[2]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[2]_PORT_B_write_enable_reg = DFFE(P1_q_a[2]_PORT_B_write_enable, P1_q_a[2]_clock_1, , , );
P1_q_a[2]_clock_0 = !RE;
P1_q_a[2]_clock_1 = !WE;
P1_q_a[2]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[2]_PORT_A_data_out = MEMORY(P1_q_a[2]_PORT_A_data_in_reg, P1_q_a[2]_PORT_B_data_in_reg, P1_q_a[2]_PORT_A_address_reg, P1_q_a[2]_PORT_B_address_reg, P1_q_a[2]_PORT_A_write_enable_reg, P1_q_a[2]_PORT_B_write_enable_reg, , , P1_q_a[2]_clock_0, P1_q_a[2]_clock_1, P1_q_a[2]_clock_enable_0, , , );
P1_q_a[2]_PORT_A_data_out_reg = DFFE(P1_q_a[2]_PORT_A_data_out, P1_q_a[2]_clock_0, , , P1_q_a[2]_clock_enable_0);
P1_q_a[13] = P1_q_a[2]_PORT_A_data_out_reg[1];


--E1L31 is MUX:inst10|O1~523 at LCCOMB_X22_Y5_N28
E1L31 = P1_q_a[2] & (CS # !Addr[0]);


--R1_dffe10a[2] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[2] at LCFF_X19_Y7_N21
R1_dffe10a[2] = DFFEAS(R1L27, !WE,  ,  ,  ,  ,  ,  ,  );


--R1_dffe10a[4] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[4] at LCFF_X19_Y7_N23
R1_dffe10a[4] = DFFEAS(UNCONNECTED_DATAIN, !WE,  ,  ,  , R1_dffe9a[4],  ,  , VCC);


--M1_power_modified_counter_values[4] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[4] at LCFF_X19_Y5_N19
M1_power_modified_counter_values[4] = DFFEAS(M1_countera4, !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[2] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[2] at LCFF_X19_Y5_N15
M1_power_modified_counter_values[2] = DFFEAS(M1_countera2, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L58 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~77 at LCCOMB_X19_Y7_N22
H1L58 = R1_dffe10a[2] & M1_power_modified_counter_values[2] & (M1_power_modified_counter_values[4] $ !R1_dffe10a[4]) # !R1_dffe10a[2] & !M1_power_modified_counter_values[2] & (M1_power_modified_counter_values[4] $ !R1_dffe10a[4]);


--R1_dffe10a[8] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[8] at LCFF_X18_Y5_N27
R1_dffe10a[8] = DFFEAS(R1L36, !WE,  ,  ,  ,  ,  ,  ,  );


--R1_dffe10a[10] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[10] at LCFF_X18_Y5_N19
R1_dffe10a[10] = DFFEAS(UNCONNECTED_DATAIN, !WE,  ,  ,  , R1_dffe9a[10],  ,  , VCC);


--M1_power_modified_counter_values[10] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[10] at LCFF_X19_Y5_N31
M1_power_modified_counter_values[10] = DFFEAS(M1_countera10, !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[8] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[8] at LCFF_X19_Y5_N27
M1_power_modified_counter_values[8] = DFFEAS(M1_countera8, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L59 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~78 at LCCOMB_X18_Y5_N18
H1L59 = M1_power_modified_counter_values[8] & R1_dffe10a[8] & (M1_power_modified_counter_values[10] $ !R1_dffe10a[10]) # !M1_power_modified_counter_values[8] & !R1_dffe10a[8] & (M1_power_modified_counter_values[10] $ !R1_dffe10a[10]);


--R1_dffe10a[9] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[9] at LCFF_X22_Y8_N3
R1_dffe10a[9] = DFFEAS(R1L38, !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[9] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[9] at LCFF_X19_Y5_N29
M1_power_modified_counter_values[9] = DFFEAS(M1_countera9, !WE,  ,  ,  ,  ,  ,  ,  );


--R1_dffe10a[0] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[0] at LCFF_X22_Y8_N31
R1_dffe10a[0] = DFFEAS(UNCONNECTED_DATAIN, !WE,  ,  ,  , R1_dffe9a[0],  ,  , VCC);


--M1_counter_ffa[0] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|counter_ffa[0] at LCFF_X19_Y5_N11
M1_counter_ffa[0] = DFFEAS(M1_countera0, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L60 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~79 at LCCOMB_X22_Y8_N30
H1L60 = M1_power_modified_counter_values[9] & R1_dffe10a[9] & (R1_dffe10a[0] $ M1_counter_ffa[0]) # !M1_power_modified_counter_values[9] & !R1_dffe10a[9] & (R1_dffe10a[0] $ M1_counter_ffa[0]);


--R1_dffe10a[6] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[6] at LCFF_X19_Y7_N9
R1_dffe10a[6] = DFFEAS(R1L33, !WE,  ,  ,  ,  ,  ,  ,  );


--R1_dffe10a[7] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[7] at LCFF_X19_Y5_N7
R1_dffe10a[7] = DFFEAS(UNCONNECTED_DATAIN, !WE,  ,  ,  , R1_dffe9a[7],  ,  , VCC);


--M1_power_modified_counter_values[7] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[7] at LCFF_X19_Y5_N25
M1_power_modified_counter_values[7] = DFFEAS(M1_countera7, !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[6] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[6] at LCFF_X19_Y5_N23
M1_power_modified_counter_values[6] = DFFEAS(M1_countera6, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L61 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~80 at LCCOMB_X19_Y5_N6
H1L61 = M1_power_modified_counter_values[7] & R1_dffe10a[7] & (M1_power_modified_counter_values[6] $ !R1_dffe10a[6]) # !M1_power_modified_counter_values[7] & !R1_dffe10a[7] & (M1_power_modified_counter_values[6] $ !R1_dffe10a[6]);


--H1L62 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~81 at LCCOMB_X19_Y5_N4
H1L62 = H1L60 & H1L59 & H1L58 & H1L61;


--R1_dffe10a[3] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[3] at LCFF_X21_Y8_N25
R1_dffe10a[3] = DFFEAS(R1L29, !WE,  ,  ,  ,  ,  ,  ,  );


--R1_dffe10a[1] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[1] at LCFF_X18_Y5_N15
R1_dffe10a[1] = DFFEAS(UNCONNECTED_DATAIN, !WE,  ,  ,  , R1_dffe9a[1],  ,  , VCC);


--M1_power_modified_counter_values[1] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[1] at LCFF_X19_Y5_N13
M1_power_modified_counter_values[1] = DFFEAS(M1_countera1, !WE,  ,  ,  ,  ,  ,  ,  );


--M1_power_modified_counter_values[3] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[3] at LCFF_X19_Y5_N17
M1_power_modified_counter_values[3] = DFFEAS(M1_countera3, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L63 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~82 at LCCOMB_X18_Y5_N14
H1L63 = M1_power_modified_counter_values[3] & R1_dffe10a[3] & (M1_power_modified_counter_values[1] $ !R1_dffe10a[1]) # !M1_power_modified_counter_values[3] & !R1_dffe10a[3] & (M1_power_modified_counter_values[1] $ !R1_dffe10a[1]);


--R1_dffe10a[5] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8|dffe10a[5] at LCFF_X19_Y5_N3
R1_dffe10a[5] = DFFEAS(UNCONNECTED_DATAIN, !WE,  ,  ,  , R1_dffe9a[5],  ,  , VCC);


--M1_power_modified_counter_values[5] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|a_graycounter_ik6:wrptr_g1p|power_modified_counter_values[5] at LCFF_X19_Y5_N21
M1_power_modified_counter_values[5] = DFFEAS(M1_countera5, !WE,  ,  ,  ,  ,  ,  ,  );


--H1L57 is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|wrfull_eq_comp_aeb_int~0 at LCCOMB_X19_Y5_N2
H1L57 = H1L62 & H1L63 & (M1_power_modified_counter_values[5] $ !R1_dffe10a[5]);


--E1L32 is MUX:inst10|O1~524 at LCCOMB_X22_Y5_N30
E1L32 = !CS & Addr[0];