fpga_dsp_portlink.fit.eqn

implemention of FPGA and DSP linking port, using Asynchronous mode

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--D1L1 is en_blk:inst8|To_DSP_En~19 at LCCOMB_X30_Y5_N0
D1L1 = !CS & (Addr[0] # Addr[1]);


--E1L18 is MUX:inst10|O1~510 at LCCOMB_X30_Y5_N6
E1L18 = P1_q_a[15] & (CS # !Addr[0]);


--E1L19 is MUX:inst10|O1~511 at LCCOMB_X30_Y5_N26
E1L19 = P1_q_a[14] & (CS # !Addr[0]);


--E1L20 is MUX:inst10|O1~512 at LCCOMB_X30_Y5_N22
E1L20 = P1_q_a[13] & (CS # !Addr[0]);


--E1L21 is MUX:inst10|O1~513 at LCCOMB_X30_Y5_N12
E1L21 = P1_q_a[12] & (CS # !Addr[0]);


--P1_q_a[11] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[11] at M4K_X27_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[11]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_a[11]_PORT_A_data_in_reg = DFFE(P1_q_a[11]_PORT_A_data_in, P1_q_a[11]_clock_0, , , P1_q_a[11]_clock_enable_0);
P1_q_a[11]_PORT_B_data_in = BUS(A1L27, A1L23);
P1_q_a[11]_PORT_B_data_in_reg = DFFE(P1_q_a[11]_PORT_B_data_in, P1_q_a[11]_clock_1, , , );
P1_q_a[11]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[11]_PORT_A_address_reg = DFFE(P1_q_a[11]_PORT_A_address, P1_q_a[11]_clock_0, , , P1_q_a[11]_clock_enable_0);
P1_q_a[11]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[11]_PORT_B_address_reg = DFFE(P1_q_a[11]_PORT_B_address, P1_q_a[11]_clock_1, , , );
P1_q_a[11]_PORT_A_write_enable = GND;
P1_q_a[11]_PORT_A_write_enable_reg = DFFE(P1_q_a[11]_PORT_A_write_enable, P1_q_a[11]_clock_0, , , P1_q_a[11]_clock_enable_0);
P1_q_a[11]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[11]_PORT_B_write_enable_reg = DFFE(P1_q_a[11]_PORT_B_write_enable, P1_q_a[11]_clock_1, , , );
P1_q_a[11]_clock_0 = !RE;
P1_q_a[11]_clock_1 = !WE;
P1_q_a[11]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[11]_PORT_A_data_out = MEMORY(P1_q_a[11]_PORT_A_data_in_reg, P1_q_a[11]_PORT_B_data_in_reg, P1_q_a[11]_PORT_A_address_reg, P1_q_a[11]_PORT_B_address_reg, P1_q_a[11]_PORT_A_write_enable_reg, P1_q_a[11]_PORT_B_write_enable_reg, , , P1_q_a[11]_clock_0, P1_q_a[11]_clock_1, P1_q_a[11]_clock_enable_0, , , );
P1_q_a[11]_PORT_A_data_out_reg = DFFE(P1_q_a[11]_PORT_A_data_out, P1_q_a[11]_clock_0, , , P1_q_a[11]_clock_enable_0);
P1_q_a[11] = P1_q_a[11]_PORT_A_data_out_reg[0];

--P1_q_a[15] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[15] at M4K_X27_Y6
P1_q_a[11]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_a[11]_PORT_A_data_in_reg = DFFE(P1_q_a[11]_PORT_A_data_in, P1_q_a[11]_clock_0, , , P1_q_a[11]_clock_enable_0);
P1_q_a[11]_PORT_B_data_in = BUS(A1L27, A1L23);
P1_q_a[11]_PORT_B_data_in_reg = DFFE(P1_q_a[11]_PORT_B_data_in, P1_q_a[11]_clock_1, , , );
P1_q_a[11]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[11]_PORT_A_address_reg = DFFE(P1_q_a[11]_PORT_A_address, P1_q_a[11]_clock_0, , , P1_q_a[11]_clock_enable_0);
P1_q_a[11]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[11]_PORT_B_address_reg = DFFE(P1_q_a[11]_PORT_B_address, P1_q_a[11]_clock_1, , , );
P1_q_a[11]_PORT_A_write_enable = GND;
P1_q_a[11]_PORT_A_write_enable_reg = DFFE(P1_q_a[11]_PORT_A_write_enable, P1_q_a[11]_clock_0, , , P1_q_a[11]_clock_enable_0);
P1_q_a[11]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[11]_PORT_B_write_enable_reg = DFFE(P1_q_a[11]_PORT_B_write_enable, P1_q_a[11]_clock_1, , , );
P1_q_a[11]_clock_0 = !RE;
P1_q_a[11]_clock_1 = !WE;
P1_q_a[11]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[11]_PORT_A_data_out = MEMORY(P1_q_a[11]_PORT_A_data_in_reg, P1_q_a[11]_PORT_B_data_in_reg, P1_q_a[11]_PORT_A_address_reg, P1_q_a[11]_PORT_B_address_reg, P1_q_a[11]_PORT_A_write_enable_reg, P1_q_a[11]_PORT_B_write_enable_reg, , , P1_q_a[11]_clock_0, P1_q_a[11]_clock_1, P1_q_a[11]_clock_enable_0, , , );
P1_q_a[11]_PORT_A_data_out_reg = DFFE(P1_q_a[11]_PORT_A_data_out, P1_q_a[11]_clock_0, , , P1_q_a[11]_clock_enable_0);
P1_q_a[15] = P1_q_a[11]_PORT_A_data_out_reg[1];


--E1L22 is MUX:inst10|O1~514 at LCCOMB_X30_Y5_N8
E1L22 = P1_q_a[11] & (CS # !Addr[0]);


--E1L23 is MUX:inst10|O1~515 at LCCOMB_X30_Y5_N2
E1L23 = P1_q_a[10] & (CS # !Addr[0]);


--E1L24 is MUX:inst10|O1~516 at LCCOMB_X30_Y5_N30
E1L24 = P1_q_a[9] & (CS # !Addr[0]);


--P1_q_a[8] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[8] at M4K_X11_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[8]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_a[8]_PORT_A_data_in_reg = DFFE(P1_q_a[8]_PORT_A_data_in, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[8]_PORT_B_data_in = BUS(A1L30, A1L24);
P1_q_a[8]_PORT_B_data_in_reg = DFFE(P1_q_a[8]_PORT_B_data_in, P1_q_a[8]_clock_1, , , );
P1_q_a[8]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[8]_PORT_A_address_reg = DFFE(P1_q_a[8]_PORT_A_address, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[8]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[8]_PORT_B_address_reg = DFFE(P1_q_a[8]_PORT_B_address, P1_q_a[8]_clock_1, , , );
P1_q_a[8]_PORT_A_write_enable = GND;
P1_q_a[8]_PORT_A_write_enable_reg = DFFE(P1_q_a[8]_PORT_A_write_enable, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[8]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[8]_PORT_B_write_enable_reg = DFFE(P1_q_a[8]_PORT_B_write_enable, P1_q_a[8]_clock_1, , , );
P1_q_a[8]_clock_0 = !RE;
P1_q_a[8]_clock_1 = !WE;
P1_q_a[8]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[8]_PORT_A_data_out = MEMORY(P1_q_a[8]_PORT_A_data_in_reg, P1_q_a[8]_PORT_B_data_in_reg, P1_q_a[8]_PORT_A_address_reg, P1_q_a[8]_PORT_B_address_reg, P1_q_a[8]_PORT_A_write_enable_reg, P1_q_a[8]_PORT_B_write_enable_reg, , , P1_q_a[8]_clock_0, P1_q_a[8]_clock_1, P1_q_a[8]_clock_enable_0, , , );
P1_q_a[8]_PORT_A_data_out_reg = DFFE(P1_q_a[8]_PORT_A_data_out, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[8] = P1_q_a[8]_PORT_A_data_out_reg[0];

--P1_q_a[14] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[14] at M4K_X11_Y6
P1_q_a[8]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_a[8]_PORT_A_data_in_reg = DFFE(P1_q_a[8]_PORT_A_data_in, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[8]_PORT_B_data_in = BUS(A1L30, A1L24);
P1_q_a[8]_PORT_B_data_in_reg = DFFE(P1_q_a[8]_PORT_B_data_in, P1_q_a[8]_clock_1, , , );
P1_q_a[8]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[8]_PORT_A_address_reg = DFFE(P1_q_a[8]_PORT_A_address, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[8]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[8]_PORT_B_address_reg = DFFE(P1_q_a[8]_PORT_B_address, P1_q_a[8]_clock_1, , , );
P1_q_a[8]_PORT_A_write_enable = GND;
P1_q_a[8]_PORT_A_write_enable_reg = DFFE(P1_q_a[8]_PORT_A_write_enable, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[8]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[8]_PORT_B_write_enable_reg = DFFE(P1_q_a[8]_PORT_B_write_enable, P1_q_a[8]_clock_1, , , );
P1_q_a[8]_clock_0 = !RE;
P1_q_a[8]_clock_1 = !WE;
P1_q_a[8]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[8]_PORT_A_data_out = MEMORY(P1_q_a[8]_PORT_A_data_in_reg, P1_q_a[8]_PORT_B_data_in_reg, P1_q_a[8]_PORT_A_address_reg, P1_q_a[8]_PORT_B_address_reg, P1_q_a[8]_PORT_A_write_enable_reg, P1_q_a[8]_PORT_B_write_enable_reg, , , P1_q_a[8]_clock_0, P1_q_a[8]_clock_1, P1_q_a[8]_clock_enable_0, , , );
P1_q_a[8]_PORT_A_data_out_reg = DFFE(P1_q_a[8]_PORT_A_data_out, P1_q_a[8]_clock_0, , , P1_q_a[8]_clock_enable_0);
P1_q_a[14] = P1_q_a[8]_PORT_A_data_out_reg[1];


--E1L25 is MUX:inst10|O1~517 at LCCOMB_X30_Y5_N10
E1L25 = P1_q_a[8] & (CS # !Addr[0]);


--E1L26 is MUX:inst10|O1~518 at LCCOMB_X30_Y5_N28
E1L26 = P1_q_a[7] & (CS # !Addr[0]);


--P1_q_a[6] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[6] at M4K_X27_Y5
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 16, Port B Logical Depth: 2048, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
P1_q_a[6]_PORT_A_data_in = BUS(VCC, VCC);
P1_q_a[6]_PORT_A_data_in_reg = DFFE(P1_q_a[6]_PORT_A_data_in, P1_q_a[6]_clock_0, , , P1_q_a[6]_clock_enable_0);
P1_q_a[6]_PORT_B_data_in = BUS(A1L32, A1L31);
P1_q_a[6]_PORT_B_data_in_reg = DFFE(P1_q_a[6]_PORT_B_data_in, P1_q_a[6]_clock_1, , , );
P1_q_a[6]_PORT_A_address = BUS(K1_power_modified_counter_values[0], K1_power_modified_counter_values[1], K1_power_modified_counter_values[2], K1_power_modified_counter_values[3], K1_power_modified_counter_values[4], K1_power_modified_counter_values[5], K1_power_modified_counter_values[6], K1_power_modified_counter_values[7], K1_power_modified_counter_values[8], K1_power_modified_counter_values[9], K1_power_modified_counter_values[10]);
P1_q_a[6]_PORT_A_address_reg = DFFE(P1_q_a[6]_PORT_A_address, P1_q_a[6]_clock_0, , , P1_q_a[6]_clock_enable_0);
P1_q_a[6]_PORT_B_address = BUS(H1_wrptr_g[0], H1_wrptr_g[1], H1_wrptr_g[2], H1_wrptr_g[3], H1_wrptr_g[4], H1_wrptr_g[5], H1_wrptr_g[6], H1_wrptr_g[7], H1_wrptr_g[8], H1_wrptr_g[9], H1_wrptr_g[10]);
P1_q_a[6]_PORT_B_address_reg = DFFE(P1_q_a[6]_PORT_B_address, P1_q_a[6]_clock_1, , , );
P1_q_a[6]_PORT_A_write_enable = GND;
P1_q_a[6]_PORT_A_write_enable_reg = DFFE(P1_q_a[6]_PORT_A_write_enable, P1_q_a[6]_clock_0, , , P1_q_a[6]_clock_enable_0);
P1_q_a[6]_PORT_B_write_enable = !H1_valid_wrreq;
P1_q_a[6]_PORT_B_write_enable_reg = DFFE(P1_q_a[6]_PORT_B_write_enable, P1_q_a[6]_clock_1, , , );
P1_q_a[6]_clock_0 = !RE;
P1_q_a[6]_clock_1 = !WE;
P1_q_a[6]_clock_enable_0 = H1_valid_rdreq;
P1_q_a[6]_PORT_A_data_out = MEMORY(P1_q_a[6]_PORT_A_data_in_reg, P1_q_a[6]_PORT_B_data_in_reg, P1_q_a[6]_PORT_A_address_reg, P1_q_a[6]_PORT_B_address_reg, P1_q_a[6]_PORT_A_write_enable_reg, P1_q_a[6]_PORT_B_write_enable_reg, , , P1_q_a[6]_clock_0, P1_q_a[6]_clock_1, P1_q_a[6]_clock_enable_0, , , );
P1_q_a[6]_PORT_A_data_out_reg = DFFE(P1_q_a[6]_PORT_A_data_out, P1_q_a[6]_clock_0, , , P1_q_a[6]_clock_enable_0);
P1_q_a[6] = P1_q_a[6]_PORT_A_data_out_reg[0];

--P1_q_a[7] is FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3|q_a[7] at M4K_X27_Y5
P1_q_a[6]_PORT_A_data_in = BUS(VCC, VCC);