plm_map_7265.c

ST7540 Demo 下位机C程序

/**************** (c) 2000  STMicroelectronics **********************

PROJECT : USB - ST7 FULL SPEED

VERSION :  v 0.96

CREATION DATE :  01/12/2000

AUTHOR : MICROCONTROLLER DIVISION / ST Rousset

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DESCRIPTION : ST72F65 Hardware Register Mapping.

              This file contains the description of the hardware register of
              the ST72F65 IC. Variable forced to a fixed address.

              WARNING : this file need a specific LINKER configuration file !

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MODIFICATIONS :

******************************************************************************/
#include "stdtypes.h"
#include "PLM_map_7265.h"

/********************************************/
/*	                 HW Reg             */
/********************************************/
/* A PORT REGISTERS */
#pragma DATA_SEG SHORT PORTA
volatile char PADR 			@0x0000;			/* PORT A : Data	 */
volatile char PADDR         @0x0001;            /* Data Direction */
volatile char PAOR          @0x0002;            /* PORT A : OR	 */

/* B PORT REGISTERS */
#pragma DATA_SEG SHORT PORTB
volatile char PBDR          @0x0003;             /* PORT B : Data */
volatile char PBDDR         @0x0004;             /* Data Direction*/
                        
/* C PORT REGISTERS */
#pragma DATA_SEG SHORT PORTC
volatile char PCDR          @0x0006;             /* PORT C : Data */
volatile char PCDDR         @0x0007;             /* Data Direction*/
volatile char PCOR          @0x0008;             /* PORT C : OR   */

/* D PORT REGISTERS */
#pragma DATA_SEG SHORT PORTD
volatile char PDDR          @0x0009;             /* PORT D : Data  */
volatile char PDDDR         @0x000A;             /* Data Direction */
volatile char PDOR          @0x000B;            /* PORT D : OR	  */

/* E PORT REGISTERS */
#pragma DATA_SEG SHORT PORTE
volatile char PEDR          @0x000C;             /* PORT E : Data  */
volatile char PEDDR         @0x000D;             /* Data Direction */
volatile char PEOR          @0x000E;            /* PORT E : OR	  */

/* F PORT REGISTERS */
#pragma DATA_SEG SHORT PORTF
volatile char PFDR          @0x000F;             /* PORT F : Data	*/
volatile char PFDDR         @0x0010;             /* Data Direction	*/
// volatile char PFOR;                             /* PORT F : OR		*/

/* A/D CONVERTER */
#pragma DATA_SEG SHORT ADC
volatile char ADCDR         @0x0012;             /* Data Register	*/
volatile char ADCCSR        @0x0013;             /* Control/Status Register	*/

/* WATCHDOG */
#pragma DATA_SEG SHORT WDG
volatile char WDGCR         @0x0014;             /* Watchdog Control Register */           

/* DSM */
#pragma DATA_SEG SHORT DSM
volatile char PCR 			@0x0018;			 /* Power Control Register	*/

/* SPI */
#pragma DATA_SEG SHORT SPI
volatile char SPIDR         @0x0019;
volatile char SPICR         @0x001A;
volatile char SPICSR        @0x001B;

/* DTC */
#pragma DATA_SEG SHORT DTC
volatile char DTCCTRL       @0x001C;             /* DTC Control Register	*/
volatile char DTCSTATUS     @0x001D;             /* DTC Status Register	*/
volatile char DTCCRC_RESERVED @0x001E;           /* Reserved DTC CRC Register	*/
volatile char DTCPC         @0x001F;             /* DTC Program Counter Register	*/

/* TIM */
#pragma DATA_SEG SHORT TIM
volatile char TCR1          @0x0020;             /* timer control register 1 */
volatile char TCR2          @0x0021;             /* timer control register 2 */
volatile char TSR           @0x0022;             /* timer status  register   */
volatile char CRH           @0x0023;             /* timer counter H register (15:8) */
volatile char CRL           @0x0024;             /* timer counter L register (7:0) */
volatile char CHRA          @0x0025;             /* timer alternate counter H register (15:8) */
volatile char CLRA          @0x0026;             /* timer alternate counter L register (7:0) */
volatile char OCHR1         @0x0027;             /* timer output compare H register 1 */
volatile char OCLR1         @0x0028;             /* timer output compare L register 1 */
volatile char OCHR2         @0x0029;             /* timer output compare H register 2 */
volatile char OCLR2         @0x002A;             /* timer output compare L register 2 */

#pragma DATA_SEG SHORT FLASH
volatile char FCSR          @0x002B;             // Flash control status register

/* SW ITC */
#pragma DATA_SEG SHORT ITC
volatile char ITSPR0        @0x002C;             // Interrupt Software Priority Register 0
volatile char ITSPR1        @0x002D;             // Interrupt Software Priority Register 1
volatile char ITSPR2        @0x002E;             // Interrupt Software Priority Register 2
volatile char ITSPR3        @0x002F;             // Interrupt Software Priority Register 3

/* USB */
#pragma DATA_SEG SHORT USB
volatile char USBISTR       @0x0030;             /* Interrupt StaTus Register*/
volatile char USBIMR        @0x0031;             /* Interrupt Mask Register */
volatile char USBCTLR       @0x0032;             /* Control Register */
volatile char DADDR         @0x0033;             /* Device ADDress Register */
volatile char USBSR         @0x0034;             /* USB Status Register */
volatile char EP0R          @0x0035;             /* Endpoint 0 Register */
volatile char CNT0RXR       @0x0036;             /* CouNT endp. 0 Reception Register */
volatile char CNT0TXR       @0x0037;             /* CouNT endp. 0 Reception Register */
volatile char EP1RXR        @0x0038;             /* Endpoint 1 Reception Register */
volatile char CNT1RXR       @0x0039;             /* CouNT endp. 1 Reception Register */
volatile char EP1TXR        @0x003A;             /* Endpoint 1 Transmission Register */
volatile char CNT1TXR       @0x003B;             /* CouNT endp. 1 Transmission Register */
volatile char EP2RXR        @0x003C;             /* Endpoint 2 Reception Register */
volatile char CNT2RXR       @0x003D;             /* CouNT endp. 2 Reception Register */
volatile char EP2TXR        @0x003E;             /* Endpoint 2 Transmission Register */
volatile char CNT2TXR       @0x003F;             /* CouNT endp. 2 Reception Register */

/* I2C INTERFACE */
#pragma DATA_SEG SHORT I2C
volatile char I2CCR         @0x0040;             /* i2c control register */
volatile char I2CSR1        @0x0041;             /* i2c status register 1 */
volatile char I2CSR2        @0x0042;             /* i2c status register 2 */
volatile char I2CCCR        @0x0043;             /* i2c clock control register */
volatile char I2COAR1       @0x0044;             /* i2c own address register 1 */
volatile char I2COAR2       @0x0045;             /* i2c own address register 2 */
volatile char I2CDR         @0x0046;             /* i2c data register */

/* USB */
#pragma DATA_SEG SHORT USBBUFSR                 
volatile char BUFSR         @0x0047;             /* Buffer Manager status register */

/* MISCELLANEOUS */
#pragma DATA_SEG SHORT MISCR
volatile char MISCR1        @0x0049;              /* Miscellaneous Register 1	*/
volatile char MISCR2        @0x004A;              /* Miscellaneous Register 2	*/
volatile char MISCR_RESERVED @0x004B;             /* Reserved Miscellaneous Register	*/
volatile char MISCR3        @0x004C;              /* Miscellaneous Register 3	*/

/* PWM */
#pragma DATA_SEG SHORT PWM
volatile char PWM0          @0x004D;                   /* pbm: PWM 0 register */ 
volatile char BRM10         @0x004E;                   /* pbm: BRM 0 register ( for 4bit brm0 and brm1 ) */
volatile char PWM1          @0x004F;                   /* pbm: PWM 1 register */


/**************** (c) 2000  STMicroelectronics **********************/