📄 mmu.s
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cmp r4, #0 @ End of table?
moveq pc, lr @ RETURN!!!! INVALID MEMORY MAP. NO MAPPING FOR KDATA AREA!
and r2, r2, r7 @ VA needs 512MB, 1MB aligned.
and r3, r3, r8 @ PA needs 4GB, 1MB aligned.
@
@ For each MB in this table entry, compare with KDATA Virtal Address...
@
8:
cmp r2, r6 @ KDATA VA = Section VA?
beq 9f @ Found it!!! (r3) is the PA
add r2, r2, #0x00100000 @ (r2) = VA + 1MB
add r3, r3, #0x00100000 @ (r3) = PA + 1MB
sub r4, r4, #1 @ Decrement number of MB left
cmp r4, #0
bne 8b @ Map next MB
b 5b @ Get next element
9:
mov r4, r9
mov r1, r3
@ Found MemoryMap entry for .KDATA section which contains the kernel data page,
@ the first-level page table, exception vector page, etc.
@
@ (r1) = base address of bank
@ (r4) = virtual address of FirstPT
@ (r11) = ptr to MemoryMap array
15:
mov r10, #BANK_SIZE
sub r10, r10, #1 @ (r10) = mask for offset
and r10, r10, r4 @ (r10) = offset into bank for FirstPT
orr r10, r10, r1 @ (r10) = ptr to FirstPT
@ Zero out page tables & kernel data page
mov r0, #0 @ (r0-r3) = 0's to store
mov r1, #0
mov r2, #0
mov r3, #0
mov r4, r10 @ (r4) = first address to clear
add r5, r10, #KDEnd-PTs @ (r5) = last address + 1
18:
stmia r4!, {r0-r3}
stmia r4!, {r0-r3}
cmp r4, r5
blo 18b
@ Setup 2nd level page table to map the high memory area which contains the
@ first level page table, 2nd level page tables, kernel data page, etc.
add r4, r10, #HighPT-PTs @ (r4) = ptr to high page table
orr r0, r10, #0x051 @ (r0) = PTE for 64K, kr/w kr/w r/o r/o page, uncached unbuffered
str r0, [r4, #0xD0*4] @ store the entry into 8 consecutive slots
str r0, [r4, #0xD1*4]
str r0, [r4, #0xD2*4]
str r0, [r4, #0xD3*4]
@ 不需要全局第二级页表，放到每一个线程 -2004-12-28 修改
@ str r0, [r4, #0xD4*4]
@ str r0, [r4, #0xD5*4]
@ str r0, [r4, #0xD6*4]
@ str r0, [r4, #0xD7*4]
@
add r8, r10, #ExceptionVectorsArea-PTs @ (r8) = ptr to vector page
@bl OEMARMCacheMode @ places C and B bit values in r0 as set by OEM
mov r0, #0x0000000C
mov r2, r0
orr r0, r8, #0x002 @ construct the PTE
orr r0, r0, r2
str r0, [r4, #0xF0*4] @ store entry for exception vectors
orr r0, r0, #0x500 @ (r0) = PTE for 4k r/o r/o kr/w kr/w C+B page
str r0, [r4, #0xF4*4] @ store entry for abort stack
str r0, [r4, #0xF6*4] @ store entry for FIQ stack (access permissions overlap for abort and FIQ stacks, same 1k)
orr r0, r8, #0x042
orr r0, r0, r2 @ (r0)= PTE for 4K r/o kr/w r/o r/o (C+B as set by OEM)
str r0, [r4, #0xF2*4] @ store entry for interrupt stack
add r9, r10, #KPage-PTs @ (r9) = ptr to kdata page
orr r0, r9, #0x002
orr r0, r0, r2 @ (r0)=PTE for 4K (C+B as set by OEM)
orr r0, r0, #0x250 @ (r0) = set perms kr/w kr/w kr/w+ur/o r/o
str r0, [r4, #0xFC*4] @ store entry for kernel data page
orr r0, r4, #0x001 @ (r0) = 1st level PTE for high memory section
add r1, r10, #0x4000
str r0, [r1, #-4] @ store PTE in last slot of 1st level table
.if 0
mov r0, r4
mov r1, #256 @ dump 256 words
CALL WriteHex
.endif
@ Fill in first level page table entries to create "un-mapped" regions
@ from the contents of the MemoryMap array.
@
@ (r9) = ptr to KData page
@ (r10) = ptr to 1st level page table
@ (r11) = ptr to MemoryMap array
add r10, r10, #0x2000 @ (r10) = ptr to 1st PTE for "unmapped space"
mov r0, #0x02
orr r0, r0, r2 @ (r0)=PTE for 0: 1MB (C+B as set by OEM)
orr r0, r0, #0x400 @ set kernel r/w permission
20:
mov r1, r11 @ (r1) = ptr to MemoryMap array
25:
ldr r2, [r1], #4 @ (r2) = virtual address to map Bank at
ldr r3, [r1], #4 @ (r3) = physical address to map from
ldr r4, [r1], #4 @ (r4) = num MB to map
cmp r4, #0 @ End of table?
beq 29f
ldr r5, =0x1FF00000
and r2, r2, r5 @ VA needs 512MB, 1MB aligned.
ldr r5, =0xFFF00000
and r3, r3, r5 @ PA needs 4GB, 1MB aligned.
add r2, r10, r2, LSR #18
add r0, r0, r3 @ (r0) = PTE for next physical page
28:
str r0, [r2], #4
add r0, r0, #0x00100000 @ (r0) = PTE for next physical page
sub r4, r4, #1 @ Decrement number of MB left
cmp r4, #0
bne 28b @ Map next MB
bic r0, r0, #0xF0000000 @ Clear Section Base Address Field
bic r0, r0, #0x0FF00000 @ Clear Section Base Address Field
b 25b @ Get next element
29:
tst r0, #8
bic r0, r0, #0x0C @ clear cachable & bufferable bits in PTE
add r10, r10, #0x0800 @ (r10) = ptr to 1st PTE for "unmapped uncached space"
bne 20b @ go setup PTEs for uncached space
sub r10, r10, #0x3000 @ (r10) = restore address of 1st level page table
@ Setup the vector area.
@
@ (r8) = ptr to exception vectors
add r7, pc, #VectorInstructions - (.+8)
ldmia r7!, {r0-r3} @ load 4 instructions
stmia r8!, {r0-r3} @ store the 4 vector instructions
ldmia r7!, {r0-r3} @ load 4 instructions
stmia r8!, {r0-r3} @ store the 4 vector instructions
@ add r8, r8, #0x3E0-(8*4)
@ ldmia r7!, {r0-r3}
@ stmia r8!, {r0-r3}
@ ldmia r7!, {r0-r3}
@ stmia r8!, {r0-r3}
@ convert VectorTable to Physical Address
ldr r0, =ES_VectorTable @ (r0) = VA of VectorTable
mov r1, r11 @ (r1) = &OEMAddressTable[0]
bl PhyAdrFromVirAdr
mov r7, r0 @ (r7) = PA of VectorTable
add r8, r8, #0x3E0-(8*4) @ (r8) = target location of the vector table
ldmia r7!, {r0-r3}
stmia r8!, {r0-r3}
ldmia r7!, {r0-r3}
stmia r8!, {r0-r3}
@ The page tables and exception vectors are setup. Initialize the MMU and turn it on.
@
mov r1, #1
mtc15 r1, c3 @ setup access to domain 0
mtc15 r10, c2
bl TLBClear
@ set mmu option
@ about test the same code with different mmu seting( timer interrupt's period is 10 ms )
@ if mmu, the cpu speed is about 88.910 seconds
@ if mmu + data cache , cpu speed is about 80.760 seconds
@ if mmu + icache, cpu speed is about 4.610 seconds
@ if mmu + dcache + icache + write buffer, cpu speed is about 3.620 seconds
@ test by lilin
mfc15 r1, c1
@ mov r1, #0 @r1 = 0
@-----fast begin--------------------------
orr r1, r1, #0x007F @ changed to read-mod-write for ARM920 Enable: MMU, Align, DCache, WriteBuffer
orr r1, r1, #0x0200 @ ROM protection enable
orr r1, r1, #0x1000 @ ICache enable
@-----fast end--------------------------
@-----medium begin--------------------------
@orr r1, r1, #0x1 @ enable mmu
@orr r1, r1, #0x0004 @ enable data cache
@orr r1, r1, #0x1000 @ Enable icache
@orr r1, r1, #0x0008 @ Enable write buffer=8
@orr r1, r1, #0x0200 @ ROM protection enable
@----medium end----------------------------
@-----slow begin--------------------------
@orr r1, r1, #0x1 @ enable mmu
@orr r1, r1, #0x0200 @ ROM protection enable
@-----slow end--------------------------
orr r1, r1, #0x2000 @ interrupt base address = 0xffff0000
@ kkkk:
@ ldr r0, =0xaadefdd
@ bl PutHex
@ b kkkk
ldr r0, VirtualStart
cmp r0, #0 @ make sure no stall on "mov pc,r0" below
mtc15 r1, c1 @ enable the MMU & Caches
mov pc, r0 @ & jump to new virtual address
nop
@ MMU & caches now enabled.
@
@ (r10) = physcial address of 1st level page table
VStart:
ldr sp, =KStack
add r4, sp, #KData-KStack @ (r4) = ptr to KDataStruct
@mov r0, #0x80000000
@str r0, [r4, #hBase] @ set HandleBase
@ldr r0, =DirectRet
@str r0, [r4, #pAPIReturn] @ set DirectReturn address
@add r1, r10, #0x4000 @ (r1) = physical addr of 2nd page table pool
@orr r1, r1, #1 @ (r1) = page table descriptor for pool entries
@str r1, [r4, #ptDesc] @ save for LoadPageTable()
@ Initialize stacks for each mode.
mov r1, #ABORT_MODE | 0x80
msr cpsr_c, r1 @ switch to Abort Mode w/IRQs disabled
add sp, r4, #AbortStack-KData
mov r1, sp @ r1 = abort sp
mov r2, #IRQ_MODE | 0x80
msr cpsr_c, r2 @ switch to IRQ Mode w/IRQs disabled
add sp, r4, #IntStack-KData
mov r2, sp @ r2 = irq sp
mov r3, #FIQ_MODE | 0x80
msr cpsr_c, r3 @ switch to FIQ Mode w/IRQs disabled
add sp, r4, #FIQStack-KData
mov r3, #UNDEF_MODE | 0x80
msr cpsr_c, r3 @ switch to Undefined Mode w/IRQs disabled
mov sp, r4 @ (sp_undef) = &KData
mov r3, sp
@ mov r3, #SVC_MODE | 0x80
@ msr cpsr_c, r3 @ switch to svc Mode w/IRQs disabled
@ mov r0, sp @ (sp_undef) = &KData
@ sub r0, r0, #0x20
mov r3, #SYS_MODE | 0x80
msr cpsr_c, r3 @ switch to Supervisor Mode w/IRQs enabled
@ mov sp, r0
ldr sp, =KDBase
mov r3, sp @ r3 = sys sp
mov r0, r10 @ r0 = first levle page table phycial address
b _InitKernel
.type VirtualStart, #object
VirtualStart: .word VStart
.size VirtualStart, . - VirtualStart
@VirtualStart DCD VStart
VectorInstructions:
ldr pc, [pc, #0x3E0-8] @ undefined instruction
@BREAKPOINT @ undefined instruction
ldr pc, [pc, #0x3E0-8] @ undefined instruction
ldr pc, [pc, #0x3E0-8] @ SVC
ldr pc, [pc, #0x3E0-8] @ Prefetch abort
ldr pc, [pc, #0x3E0-8] @ data abort
@BREAKPOINT @ unused vector location
ldr pc, [pc, #0x3E0-8] @ unused vector location
ldr pc, [pc, #0x3E0-8] @ IRQ
ldr pc, [pc, #0x3E0-8] @ FIQ
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