qdq.twr

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml qdq qdq.ncd -o qdq.twr
qdq.pcf


Design file:              qdq.ncd
Physical constraint file: qdq.pcf
Device,speed:             xc2s100,-6 (PRODUCTION 1.27 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clkin
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
en          |    3.514(R)|   -1.748(R)|clkin_BUFGP       |   0.000|
en1         |    3.663(R)|   -1.897(R)|clkin_BUFGP       |   0.000|
qqd<0>      |    8.096(R)|   -3.386(R)|clkin_BUFGP       |   0.000|
qqd<1>      |    9.536(R)|   -4.792(R)|clkin_BUFGP       |   0.000|
qqd<2>      |    8.672(R)|   -3.914(R)|clkin_BUFGP       |   0.000|
qqd<3>      |    8.155(R)|   -4.493(R)|clkin_BUFGP       |   0.000|
qqd<4>      |    7.920(R)|   -4.661(R)|clkin_BUFGP       |   0.000|
qqd<5>      |    9.697(R)|   -5.643(R)|clkin_BUFGP       |   0.000|
qqd<6>      |    9.018(R)|   -5.212(R)|clkin_BUFGP       |   0.000|
qqd<7>      |    9.041(R)|   -4.938(R)|clkin_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock clkin to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
q1          |    8.906(R)|clkin_BUFGP       |   0.000|
states<0>   |    6.385(R)|clkin_BUFGP       |   0.000|
states<1>   |    6.370(R)|clkin_BUFGP       |   0.000|
states<2>   |    6.370(R)|clkin_BUFGP       |   0.000|
states<3>   |    6.369(R)|clkin_BUFGP       |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clkin
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clkin          |    4.158|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Wed Jun 13 11:02:23 2007
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Peak Memory Usage: 47 MB