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Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)Phase 1.1Phase 1.1 (Checksum:9899af) REAL time: 0 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8.Phase 5.8 (Checksum:9a261b) REAL time: 0 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file top.ncd.Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 560 unrouted; REAL time: 0 secs Phase 2: 520 unrouted; REAL time: 4 secs Phase 3: 97 unrouted; REAL time: 4 secs Phase 4: 0 unrouted; REAL time: 4 secs Total REAL time to Router completion: 4 secs Total CPU time to Router completion: 3 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+| Clock Net | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+| clkin_BUFGP | Global | 20 | 0.088 | 0.502 |+----------------------------+----------+--------+------------+-------------+| XLXI_14_clk | Local | 32 | 1.715 | 3.199 |+----------------------------+----------+--------+------------+-------------+Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 5 secs Total CPU time to PAR completion: 4 secs Peak Memory Usage: 55 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file top.ncd.PAR done.Completed process "Place & Route".Started process "Generate Post-Place & Route Static Timing".WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This generally indicates that there is an inconsistency between versions of the speed and device data files. Please check to ensure that the XILINX environment variable is set correctly, if the MYXILINX variable is set, make sure that it is pointing to patch files that are compatable with the version of software that the XILINX variable points to.WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This generally indicates that there is an inconsistency between versions of the speed and device data files. Please check to ensure that the XILINX environment variable is set correctly, if the MYXILINX variable is set, make sure that it is pointing to patch files that are compatable with the version of software that the XILINX variable points to.Analysis completed Wed Jun 13 08:53:44 2007--------------------------------------------------------------------------------Generating Report ...Completed process "Generate Post-Place & Route Static Timing".Place & Route Module top . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
PAR completed successfully
Started process "Programming File Generation Report".Completed process "Programming File Generation Report".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd e:\王健根2401102016\top/_ngo -uctop.ucf -p xc2s100-pq208-6 top.ngc top.ngd Reading NGO file "E:/王健根2401102016/TOP/top.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "top.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 41448 kilobytesWriting NGD file "top.ngd" ...Writing NGDBUILD log file "top.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "2s100pq208-6".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 0Logic Utilization: Number of Slice Flip Flops: 76 out of 2,400 3% Number of 4 input LUTs: 116 out of 2,400 4%Logic Distribution: Number of occupied Slices: 94 out of 1,200 7% Number of Slices containing only related logic: 94 out of 94 100% Number of Slices containing unrelated logic: 0 out of 94 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 160 out of 2,400 6% Number used as logic: 116 Number used as a route-thru: 44 Number of bonded IOBs: 31 out of 140 22% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 1,652Additional JTAG gate count for IOBs: 1,536Peak Memory Usage: 61 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "top_map.mrp" for details.Completed process "Map".Mapping Module top . . .
MAP command line:
map -intstyle ise -p xc2s100-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf
Mapping Module top: DONE
Started process "Place & Route".Constraints file: top.pcfLoading device database for application Par from file "top_map.ncd". "top" is an NCD, version 2.38, device xc2s100, package pq208, speed -6Loading device for application Par from file 'v100.nph' in environmentC:/Xilinx.Device speed data version: PRODUCTION 1.27 2003-12-13.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 31 out of 140 22% Number of LOCed External IOBs 31 out of 31 100% Number of SLICEs 94 out of 1200 7% Number of GCLKs 1 out of 4 25%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)Phase 1.1Phase 1.1 (Checksum:9899af) REAL time: 0 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8.Phase 5.8 (Checksum:9a17c0) REAL time: 0 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file top.ncd.Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 560 unrouted; REAL time: 0 secs Phase 2: 511 unrouted; REAL time: 4 secs Phase 3: 108 unrouted; REAL time: 4 secs Phase 4: 0 unrouted; REAL time: 4 secs Total REAL time to Router completion: 4 secs Total CPU time to Router completion: 4 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+| Clock Net | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+| clkin_BUFGP | Global | 20 | 0.082 | 0.501 |+----------------------------+----------+--------+------------+-------------+| XLXI_14_clk | Local | 32 | 1.684 | 3.188 |+----------------------------+----------+--------+------------+-------------+Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 4 secs Peak Memory Usage: 55 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file top.ncd.PAR done.Completed process "Place & Route".Started process "Generate Post-Place & Route Static Timing".WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This generally indicates that there is an inconsistency between versions of the speed and device data files. Please check to ensure that the XILINX environment variable is set correctly, if the MYXILINX variable is set, make sure that it is pointing to patch files that are compatable with the version of software that the XILINX variable points to.WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This generally indicates that there is an inconsistency between versions of the speed and device data files. Please check to ensure that the XILINX environment variable is set correctly, if the MYXILINX variable is set, make sure that it is pointing to patch files that are compatable with the version of software that the XILINX variable points to.Analysis completed Wed Jun 13 09:04:21 2007--------------------------------------------------------------------------------Generating Report ...Completed process "Generate Post-Place & Route Static Timing".Place & Route Module top . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
PAR completed successfully
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd e:\王健根2401102016\top/_ngo -uctop.ucf -p xc2s100-pq208-6 top.ngc top.ngd Reading NGO file "E:/王健根2401102016/TOP/top.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "top.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 41448 kilobytesWriting NGD file "top.ngd" ...Writing NGDBUILD log file "top.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "2s100pq208-6".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 0Logic Utilization: Number of Slice Flip Flops: 76 out of 2,400 3% Number of 4 input LUTs: 116 out of 2,400 4%Logic Distribution: Number of occupied Slices: 94 out of 1,200 7% Number of Slices containing only related logic: 94 out of 94 100% Number of Slices containing unrelated logic: 0 out of 94 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 160 out of 2,400 6% Number used as logic: 116 Number used as a route-thru: 44 Number of bonded IOBs: 31 out of 140 22% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 1,652Additional JTAG gate count for IOBs: 1,536Peak Memory Usage: 61 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "top_map.mrp" for details.Completed proc⌨️ 快捷键说明
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