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Compiling vhdl file E:/王健根2401102016/TOP/qdq.vhdl in Library work.
Entity <qdq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl testbench file generated.


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Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".




Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/TOP is now defined in a different file: was D:/xilinx仿真/王健根2401102016/TOP/top.vhf, now is E:/王健根2401102016/TOP/top.vhf
WARNING:HDLParsers:3215 - Unit work/TOP/BEHAVIORAL is now defined in a different file: was D:/xilinx仿真/王健根2401102016/TOP/top.vhf, now is E:/王健根2401102016/TOP/top.vhf
WARNING:HDLParsers:3215 - Unit work/FPQ is now defined in a different file: was D:/xilinx仿真/王健根2401102016/TOP/fpq.vhdl, now is E:/王健根2401102016/TOP/fpq.vhdl
WARNING:HDLParsers:3215 - Unit work/FPQ/BEHAVIORAL is now defined in a different file: was D:/xilinx仿真/王健根2401102016/TOP/fpq.vhdl, now is E:/王健根2401102016/TOP/fpq.vhdl
WARNING:HDLParsers:3215 - Unit work/DSQ is now defined in a different file: was D:/xilinx仿真/王健根2401102016/TOP/dsq.vhdl, now is E:/王健根2401102016/TOP/dsq.vhdl
WARNING:HDLParsers:3215 - Unit work/DSQ/BEHAVIORAL is now defined in a different file: was D:/xilinx仿真/王健根2401102016/TOP/dsq.vhdl, now is E:/王健根2401102016/TOP/dsq.vhdl
WARNING:HDLParsers:3215 - Unit work/BJQ is now defined in a different file: was D:/xilinx仿真/王健根2401102016/TOP/bjq.vhdl, now is E:/王健根2401102016/TOP/bjq.vhdl
WARNING:HDLParsers:3215 - Unit work/BJQ/BEHAVIORAL is now defined in a different file: was D:/xilinx仿真/王健根2401102016/TOP/bjq.vhdl, now is E:/王健根2401102016/TOP/bjq.vhdl
WARNING:HDLParsers:3215 - Unit work/YMQ is now defined in a different file: was D:/xilinx仿真/王健根2401102016/TOP/ymq.vhdl, now is E:/王健根2401102016/TOP/ymq.vhdl
WARNING:HDLParsers:3215 - Unit work/YMQ/BEHAVIORAL is now defined in a different file: was D:/xilinx仿真/王健根2401102016/TOP/ymq.vhdl, now is E:/王健根2401102016/TOP/ymq.vhdl
Compiling vhdl file E:/王健根2401102016/TOP/qdq.vhdl in Library work.
Architecture behavioral of Entity qdq is up to date.
Compiling vhdl file E:/王健根2401102016/TOP/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file E:/王健根2401102016/TOP/bjq.vhdl in Library work.
Architecture behavioral of Entity bjq is up to date.
Compiling vhdl file E:/王健根2401102016/TOP/dsq.vhdl in Library work.
Architecture behavioral of Entity dsq is up to date.
Compiling vhdl file E:/王健根2401102016/TOP/fpq.vhdl in Library work.
Architecture behavioral of Entity fpq is up to date.
Compiling vhdl file E:/王健根2401102016/TOP/top.vhf in Library work.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <qdq> (Architecture <behavioral>).
Entity <qdq> analyzed. Unit <qdq> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <bjq> (Architecture <behavioral>).
Entity <bjq> analyzed. Unit <bjq> generated.

Analyzing Entity <dsq> (Architecture <behavioral>).
Entity <dsq> analyzed. Unit <dsq> generated.

Analyzing Entity <fpq> (Architecture <behavioral>).
Entity <fpq> analyzed. Unit <fpq> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpq>.
    Related source file is E:/王健根2401102016/TOP/fpq.vhdl.
    Found 1-bit register for signal <clk>.
    Found 24-bit up counter for signal <counter>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <fpq> synthesized.


Synthesizing Unit <dsq>.
    Related source file is E:/王健根2401102016/TOP/dsq.vhdl.
    Found 10-bit adder for signal <$n0029> created at line 38.
    Found 4-bit down counter for signal <num>.
    Found 10-bit register for signal <num1>.
    Found 1-bit register for signal <q0>.
    Summary:
	inferred   1 Counter(s).
	inferred  11 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <dsq> synthesized.


Synthesizing Unit <bjq>.
    Related source file is E:/王健根2401102016/TOP/bjq.vhdl.
    Found 1-bit register for signal <bout1>.
    Found 1-bit register for signal <bout2>.
    Found 1-bit register for signal <bout3>.
    Found 8-bit down counter for signal <num1>.
    Found 8-bit down counter for signal <num2>.
    Found 8-bit down counter for signal <num3>.
    Summary:
	inferred   3 Counter(s).
	inferred   3 D-type flip-flop(s).
Unit <bjq> synthesized.


Synthesizing Unit <ymq>.
    Related source file is E:/王健根2401102016/TOP/ymq.vhdl.
    Found 16x7-bit ROM for signal <ooo>.
    Summary:
	inferred   1 ROM(s).
Unit <ymq> synthesized.


Synthesizing Unit <qdq>.
    Related source file is E:/王健根2401102016/TOP/qdq.vhdl.
    Found 1-bit register for signal <q2>.
    Found 4-bit register for signal <states1>.
    Found 4-bit register for signal <states2>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <qdq> synthesized.


Synthesizing Unit <top>.
    Related source file is E:/王健根2401102016/TOP/top.vhf.
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 3
 16x7-bit ROM                      : 3
# Adders/Subtractors               : 1
 10-bit adder                      : 1
# Counters                         : 5
 24-bit up counter                 : 1
 8-bit down counter                : 3
 4-bit down counter                : 1
# Registers                        : 9
 4-bit register                    : 2
 1-bit register                    : 6
 10-bit register                   : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...

Optimizing unit <qdq> ...

Optimizing unit <fpq> ...

Optimizing unit <bjq> ...

Optimizing unit <dsq> ...
Loading device for application Xst from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 7.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-6 

 Number of Slices:                      97  out of   1200     8%  
 Number of Slice Flip Flops:            76  out of   2400     3%  
 Number of 4 input LUTs:               158  out of   2400     6%  
 Number of bonded IOBs:                 31  out of    144    21%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clkin                              | BUFGP                  | 34    |
XLXI_14_clk:Q                      | NONE                   | 42    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.902ns (Maximum Frequency: 112.334MHz)
   Minimum input arrival time before clock: 10.791ns
   Maximum output required time after clock: 13.367ns
   Maximum combinational path delay: 11.492ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\王健根2401102016\top/_ngo -i -p
xc2s100-pq208-6 top.ngc top.ngd 

Reading NGO file "E:/王健根2401102016/TOP/top.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 39400 kilobytes

Writing NGD file "top.ngd" ...

Writing NGDBUILD log file "top.bld"...

NGDBUILD done.
Completed process "Translate".



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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\王健根2401102016\top/_ngo -uc
top.ucf -p xc2s100-pq208-6 top.ngc top.ngd 

Reading NGO file "E:/王健根2401102016/TOP/top.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "top.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 41448 kilobytes

Writing NGD file "top.ngd" ...

Writing NGDBUILD log file "top.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s100pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        76 out of  2,400    3%
  Number of 4 input LUTs:           116 out of  2,400    4%
Logic Distribution:
    Number of occupied Slices:                          94 out of  1,200    7%
    Number of Slices containing only related logic:     94 out of     94  100%
    Number of Slices containing unrelated logic:         0 out of     94    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          160 out of  2,400    6%
      Number used as logic:                       116
      Number used as a route-thru:                 44
   Number of bonded IOBs:            31 out of    140   22%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  1,652
Additional JTAG gate count for IOBs:  1,536
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "top_map.mrp" for details.
Completed process "Map".

Mapping Module top . . .
MAP command line:
map -intstyle ise -p xc2s100-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf
Mapping Module top: DONE



Started process "Place & Route".





Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc2s100, package pq208, speed -6
Loading device for application Par from file 'v100.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            31 out of 140    22%
      Number of LOCed External IOBs   31 out of 31    100%

   Number of SLICEs                   94 out of 1200    7%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9899af) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:9a350c) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs