__projnav.log

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Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
ERROR:DesignEntry:3 - Bus "XLXN_7(3:0)" and its subbus need to be connected to
   pins or IO Ports.
Error: 
Process "View VHDL Functional Model" did not complete.


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Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
ERROR:DesignEntry:3 - Bus "XLXN_7(3:0)" and its subbus need to be connected to
   pins or IO Ports.
Error: 
Process "View VHDL Functional Model" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
ERROR:DesignEntry:3 - Bus "XLXN_7(3:0)" and its subbus need to be connected to
   pins or IO Ports.

Error creating topaaa.vhd. Defaulting to boilerplate test bench.


Project Navigator Auto-Make Log File
-------------------------------------

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
ERROR:DesignEntry:3 - Bus "XLXN_7(3:0)" and its subbus need to be connected to
   pins or IO Ports.

Error creating topaaa.vhd. Defaulting to boilerplate test bench.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".



Project Navigator Auto-Make Log File
-------------------------------------

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl testbench file generated.


Project Navigator Auto-Make Log File
-------------------------------------

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl testbench file generated.


Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/fpq.vhdl in Library work.
Entity <fpq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/fpq.vhdl in Library work.
Entity <fpq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/qdq.vhdl in Library work.
Architecture behavioral of Entity qdq is up to date.
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/bjq.vhdl in Library work.
Architecture behavioral of Entity bjq is up to date.
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/dsq.vhdl in Library work.
Architecture behavioral of Entity dsq is up to date.
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/fpq.vhdl in Library work.
Architecture behavioral of Entity fpq is up to date.
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/top.vhf in Library work.
Entity <top> (Architecture <BEHAVIORAL>) compiled.
Completed process "Check Syntax".



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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/qdq.vhdl in Library work.
Entity <qdq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/dsq.vhdl in Library work.
Entity <dsq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/bjq.vhdl in Library work.
Entity <bjq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/fpq.vhdl in Library work.
Entity <fpq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
-------------------------------------

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/fpq.vhdl in Library work.
Entity <fpq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/fpq.vhdl in Library work.
Entity <fpq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/qdq.vhdl in Library work.
Architecture behavioral of Entity qdq is up to date.
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/bjq.vhdl in Library work.
Architecture behavioral of Entity bjq is up to date.
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/dsq.vhdl in Library work.
Architecture behavioral of Entity dsq is up to date.
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/fpq.vhdl in Library work.
Architecture behavioral of Entity fpq is up to date.
Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/top.vhf in Library work.
Entity <top> (Architecture <behavioral>) compiled.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl testbench file generated.


Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

WARNING:HDLParsers:3215 - Unit work/QDQ is now defined in a different file: was
   D:/xilinx仿真/王健根2401102016/TOP/qdq.vhdl, now is
   E:/王健根2401102016/TOP/qdq.vhdl
WARNING:HDLParsers:3215 - Unit work/QDQ/BEHAVIORAL is now defined in a different
   file: was D:/xilinx仿真/王健根2401102016/TOP/qdq.vhdl, now is
   E:/王健根2401102016/TOP/qdq.vhdl