__projnav.log

主持人按开始抢答后

Project Navigator Auto-Make Log File
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Compiling vhdl file d:/xilinx仿真/王健根2401102016/top/bjq.vhdl in Library work.
Entity <bjq> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
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Compiling vhdl file d:/xilinx仿真/王健根2401102016/top/dsq.vhdl in Library work.
Entity <dsq> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
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Compiling vhdl file d:/xilinx仿真/王健根2401102016/top/fpq.vhdl in Library work.
Entity <fpq> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
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Compiling vhdl file d:/xilinx仿真/王健根2401102016/top/ymq.vhdl in Library work.
Entity <ymq> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
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Compiling vhdl file d:/xilinx仿真/王健根2401102016/top/qdq.vhdl in Library work.
Entity <qdq> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Compiling vhdl file d:/xilinx仿真/王健根2401102016/top/bjq.vhdl in Library work.
Entity <bjq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Compiling vhdl file d:/xilinx仿真/王健根2401102016/top/dsq.vhdl in Library work.
Entity <dsq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Compiling vhdl file d:/xilinx仿真/王健根2401102016/top/fpq.vhdl in Library work.
Entity <fpq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file d:/xilinx仿真/王健根2401102016/top/qdq.vhdl in Library work.
Entity <qdq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file d:/xilinx仿真/王健根2401102016/top/ymq.vhdl in Library work.
Entity <ymq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
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Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl testbench file generated.


Project Navigator Auto-Make Log File
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Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".




Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/qdq.vhdl in Library work.
Entity <qdq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/ymq.vhdl in Library work.
Entity <ymq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/bjq.vhdl in Library work.
Entity <bjq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.



Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/ymq.vhdl in Library work.
Entity <ymq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/qdq.vhdl in Library work.
Entity <qdq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/bjq.vhdl in Library work.
Entity <bjq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
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Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".



Project Navigator Auto-Make Log File
-------------------------------------

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl testbench file generated.


Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/xilinx仿真/王健根2401102016/TOP/qdq.vhdl in Library work.
Entity <qdq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
WARNING:DesignEntry:11 - Net "XLXN_2" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
ERROR:DesignEntry:3 - Bus "XLXN_6(3:0)" and its subbus need to be connected to
   pins or IO Ports.
ERROR:DesignEntry:3 - Bus "XLXN_7(3:0)" and its subbus need to be connected to
   pins or IO Ports.
ERROR:DesignEntry:2 - Net "XLXN_9" needs to be connected to pins or IO Ports.
WARNING:DesignEntry:13 - Net "XLXN_11" is connected to source pins and/or IO
   ports while there is no load pin connected to it
ERROR:DesignEntry:2 - Net "bout" needs to be connected to pins or IO Ports.
ERROR:DesignEntry:3 - Bus "out72(6:0)" and its subbus need to be connected to
   pins or IO Ports.
ERROR:DesignEntry:3 - Bus "out73(6:0)" and its subbus need to be connected to
   pins or IO Ports.
Error: 
Process "View VHDL Functional Model" did not complete.


Project Navigator Auto-Make Log File
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Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
WARNING:DesignEntry:11 - Net "XLXN_2" is connected to load pins and/or IO Port,
   but there is no source pin or IO Port connected to it
ERROR:DesignEntry:3 - Bus "XLXN_6(3:0)" and its subbus need to be connected to
   pins or IO Ports.
ERROR:DesignEntry:3 - Bus "XLXN_7(3:0)" and its subbus need to be connected to
   pins or IO Ports.
ERROR:DesignEntry:2 - Net "XLXN_9" needs to be connected to pins or IO Ports.
WARNING:DesignEntry:13 - Net "XLXN_11" is connected to source pins and/or IO
   ports while there is no load pin connected to it
ERROR:DesignEntry:2 - Net "bout" needs to be connected to pins or IO Ports.
ERROR:DesignEntry:3 - Bus "out72(6:0)" and its subbus need to be connected to
   pins or IO Ports.
ERROR:DesignEntry:3 - Bus "out73(6:0)" and its subbus need to be connected to
   pins or IO Ports.

Error creating topaaa.vhd. Defaulting to boilerplate test bench.


Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".