top.twr

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml top top.ncd -o top.twr
top.pcf


Design file:              top.ncd
Physical constraint file: top.pcf
Device,speed:             xc2s100,-6 (PRODUCTION 1.27 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
en          |    1.496(R)|   -0.307(R)|clk_BUFGP         |   0.000|
qd<0>       |    5.057(R)|   -0.781(R)|clk_BUFGP         |   0.000|
qd<1>       |    5.408(R)|   -1.631(R)|clk_BUFGP         |   0.000|
qd<2>       |    4.943(R)|   -1.291(R)|clk_BUFGP         |   0.000|
qd<3>       |    4.597(R)|   -0.618(R)|clk_BUFGP         |   0.000|
qd<4>       |    4.568(R)|   -0.509(R)|clk_BUFGP         |   0.000|
qd<5>       |    4.962(R)|   -1.646(R)|clk_BUFGP         |   0.000|
qd<6>       |    4.708(R)|   -0.681(R)|clk_BUFGP         |   0.000|
qd<7>       |    4.743(R)|   -0.643(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
xuanshou<0> |   10.574(R)|clk_BUFGP         |   0.000|
xuanshou<1> |   11.235(R)|clk_BUFGP         |   0.000|
xuanshou<2> |   10.974(R)|clk_BUFGP         |   0.000|
xuanshou<3> |   11.128(R)|clk_BUFGP         |   0.000|
xuanshou<4> |   11.427(R)|clk_BUFGP         |   0.000|
xuanshou<5> |   11.261(R)|clk_BUFGP         |   0.000|
xuanshou<6> |   11.231(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    7.539|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
en             |time1<1>       |   10.832|
en             |time1<2>       |   11.626|
en             |time1<3>       |   10.910|
en             |time1<4>       |    7.688|
en             |time1<5>       |    9.101|
en             |time1<6>       |   11.387|
en             |time2<0>       |   14.194|
en             |time2<1>       |   13.781|
en             |time2<2>       |   14.240|
en             |time2<3>       |   14.579|
en             |time2<4>       |   13.897|
en             |time2<5>       |   13.294|
en             |time2<6>       |   13.354|
---------------+---------------+---------+

Analysis completed Wed Jun 27 00:05:25 2007
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Peak Memory Usage: 46 MB