qdq.syr

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Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: qdq.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : qdq.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : qdq
Output Format                      : NGC
Target Device                      : xc2s100-6-pq208

---- Source Options
Top Module Name                    : qdq
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : qdq.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/王健根2401102016/TOP/qdq.vhdl in Library work.
Architecture behavioral of Entity qdq is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <qdq> (Architecture <behavioral>).
Entity <qdq> analyzed. Unit <qdq> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <qdq>.
    Related source file is E:/王健根2401102016/TOP/qdq.vhdl.
    Found 1-bit register for signal <q2>.
    Found 4-bit register for signal <states1>.
    Found 4-bit register for signal <states2>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <qdq> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 3
 4-bit register                    : 2
 1-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <qdq> ...
Loading device for application Xst from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block qdq, actual ratio is 1.
FlipFlop q2 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : qdq.ngr
Top Level Output File Name         : qdq
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 16

Macro Statistics :
# Registers                        : 3
#      1-bit register              : 1
#      4-bit register              : 2

Cell Usage :
# BELS                             : 32
#      LUT2                        : 3
#      LUT3                        : 6
#      LUT4                        : 19
#      LUT4_L                      : 4
# FlipFlops/Latches                : 10
#      FDE                         : 4
#      FDR                         : 4
#      FDRS                        : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 15
#      IBUF                        : 10
#      OBUF                        : 5
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-6 

 Number of Slices:                      18  out of   1200     1%  
 Number of Slice Flip Flops:            10  out of   2400     0%  
 Number of 4 input LUTs:                32  out of   2400     1%  
 Number of bonded IOBs:                 15  out of    144    10%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clkin                              | BUFGP                  | 10    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.549ns (Maximum Frequency: 281.770MHz)
   Minimum input arrival time before clock: 11.385ns
   Maximum output required time after clock: 6.788ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clkin'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            states1_3 (FF)
  Destination:       states1_3 (FF)
  Source Clock:      clkin rising
  Destination Clock: clkin rising

  Data Path: states1_3 to states1_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.085   1.206  states1_3 (states1_3)
     LUT4_L:I2->LO         1   0.549   0.000  _n0004<3>1 (_n0004<3>)
     FDE:D                     0.709          states1_3
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkin'
Offset:              11.385ns (Levels of Logic = 6)
  Source:            qqd<7> (PAD)
  Destination:       q2 (FF)
  Destination Clock: clkin rising

  Data Path: qqd<7> to q2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             8   0.776   1.845  qqd_7_IBUF (qqd_7_IBUF)
     LUT3:I0->O            3   0.549   1.332  Ker7571 (N759)
     LUT3:I0->O            4   0.549   1.440  Ker7491 (N751)
     LUT4:I3->O            3   0.549   1.332  _n00121 (_n0012)
     LUT4:I3->O            2   0.549   1.206  _n00034 (CHOICE54)
     LUT2:I0->O            2   0.549   0.000  _n0003181 (N1309)
     FDRS:D                    0.709          q2
    ----------------------------------------
    Total                     11.385ns (4.230ns logic, 7.155ns route)
                                       (37.2% logic, 62.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkin'
Offset:              6.788ns (Levels of Logic = 1)
  Source:            q2_1 (FF)
  Destination:       q1 (PAD)
  Source Clock:      clkin rising

  Data Path: q2_1 to q1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRS:C->Q             1   1.085   1.035  q2_1 (q2_1)
     OBUF:I->O                 4.668          q1_OBUF (q1)
    ----------------------------------------
    Total                      6.788ns (5.753ns logic, 1.035ns route)
                                       (84.8% logic, 15.2% route)

=========================================================================
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