top.par

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Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

CC88B85591D14CF::  Wed Jun 27 00:05:17 2007


D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd
top.pcf 


Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc2s100, package pq208, speed -6
Loading device for application Par from file 'v100.nph' in environment
D:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <time2<1>> must be placed at site P89.
Resolved that IOB <time1<5>> must be placed at site P61.
Resolved that IOB <time2<2>> must be placed at site P100.
Resolved that IOB <time1<6>> must be placed at site P59.
Resolved that IOB <time2<3>> must be placed at site P99.
Resolved that IOB <time2<4>> must be placed at site P98.
Resolved that IOB <time2<5>> must be placed at site P83.
Resolved that IOB <en> must be placed at site P10.
Resolved that IOB <time2<6>> must be placed at site P87.
Resolved that GCLKIOB <clk> must be placed at site P182.
Resolved that IOB <baojing> must be placed at site P113.
Resolved that IOB <xuanshou<0>> must be placed at site P62.
Resolved that IOB <xuanshou<1>> must be placed at site P63.
Resolved that IOB <xuanshou<2>> must be placed at site P69.
Resolved that IOB <xuanshou<3>> must be placed at site P58.
Resolved that IOB <xuanshou<4>> must be placed at site P60.
Resolved that IOB <xuanshou<5>> must be placed at site P68.
Resolved that IOB <xuanshou<6>> must be placed at site P67.
Resolved that IOB <qd<0>> must be placed at site P14.
Resolved that IOB <qd<1>> must be placed at site P15.
Resolved that IOB <qd<2>> must be placed at site P16.
Resolved that IOB <qd<3>> must be placed at site P17.
Resolved that IOB <qd<4>> must be placed at site P18.
Resolved that IOB <qd<5>> must be placed at site P20.
Resolved that IOB <qd<6>> must be placed at site P21.
Resolved that IOB <time1<0>> must be placed at site P49.
Resolved that IOB <qd<7>> must be placed at site P22.
Resolved that IOB <time1<1>> must be placed at site P57.
Resolved that IOB <time1<2>> must be placed at site P46.
Resolved that IOB <time1<3>> must be placed at site P47.
Resolved that IOB <time2<0>> must be placed at site P97.
Resolved that IOB <time1<4>> must be placed at site P48.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            31 out of 140    22%
      Number of LOCed External IOBs   31 out of 31    100%

   Number of SLICEs                   90 out of 1200    7%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98998f) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.
Phase 5.8 (Checksum:99f8fd) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 549 unrouted;       REAL time: 2 secs 

Phase 2: 502 unrouted;       REAL time: 6 secs 

Phase 3: 103 unrouted;       REAL time: 6 secs 

Phase 4: 0 unrouted;       REAL time: 6 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 4 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   22   |  0.095     |  0.507      |
+----------------------------+----------+--------+------------+-------------+
|       XLXI_14_clk          |   Local  |   32   |  1.991     |  3.173      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 170


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.210
   The MAXIMUM PIN DELAY IS:                               4.258
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.461

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         295         187          27          31           9           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  54 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.