qdq.vhdl

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity qdq is
    Port ( en : in std_logic;
           clk : in std_logic;
           q2 : in std_logic;
           qiang : in std_logic_vector(7 downto 0);
           qz : out std_logic_vector(3 downto 0);
           q1 : out std_logic);
end qdq;

architecture Behavioral of qdq is

  signal Y_s:std_logic_vector(3 downto 0);
  signal Q:std_logic;
  signal G1:std_logic;
begin
  process(clk,qiang,en,Y_s,q2)
    begin 
	if (en='0') then
	 	 G1<='1'; q1<='0';qz<="0000"; Q<='0'; 

	   elsif clk'event and clk='1' then 
	   
	      case qiang is
	     
		  when "10000000" => Y_s <= "0001";Q<='1';
		  when "01000000" => Y_s <= "0010";Q<='1';
		  when "00100000" => Y_s <= "0011"; Q<='1';
		  when "00010000" => Y_s <= "0100"; Q<='1';
		  when "00001000" => Y_s <= "0101"; Q<='1';
		  when "00000100" => Y_s <= "0110"; Q<='1';
		  when "00000010" => Y_s <= "0111"; Q<='1';
		  when "00000001" => Y_s <= "1000"; Q<='1';
		  when others => Y_s <= "0000";
		
		end case;
	    	if (G1 and Q and (not q2))='1' then 
	       qz<=Y_s;	q1<=Q;G1<='0';
		 elsif G1='1' then
		  qz<="0000";   
		end if;

	 end if;

  end process;


end Behavioral;