bjq.vhdl

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bjq is 
   port 
     (b1,b2,b3,clkin1:in std_logic;
	    bout:out std_logic);
end bjq;
architecture Behavioral of bjq is
    signal num1:integer range 0 to 160;
    signal num2:integer range 0 to 160;
    signal num3:integer range 0 to 160;
    signal bout1,bout2,bout3: std_logic;
 begin 
      bout<=bout1 and bout2 and bout3 ;    
    process(b1,clkin1) is
      begin
 	       if b1='1' then 
	          if rising_edge(clkin1) then 
		         if num1/=0 then
		           num1<=num1-1;
		           bout1<='0';
		         else  bout1<='1';
		         end if;
		       end if;
	      else bout1<='1';num1<=160;
	      end if;
	 end process;
   process(b2,clkin1) is
     begin
 	      if b2='1' then 
	         if rising_edge(clkin1) then 
		         if num2/=0 then
		           num2<=num2-1;
		           bout2<='0';
		         else  bout2<='1';
		         end if;
           end if;
		  else bout2<='1';num2<=160;
	    end if;
	end process;
  process(b3,clkin1) is
     begin
 	      if b3='1' then 
	         if rising_edge(clkin1) then
		        if num3/=0 then
		          num3<=num3-1;
		          bout3<='0';
		        else   bout3<='1';
             end if;
           end if;
		   else bout3<='1';num3<=160;
	     end if;
end process;

   end Behavioral;