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Optimizing unit <bjq> ...

Optimizing unit <dsq> ...
Loading device for application Xst from file 'v100.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 7.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 32

Macro Statistics :
# ROMs                             : 3
#      16x7-bit ROM                : 3
# Registers                        : 51
#      1-bit register              : 48
#      10-bit register             : 1
#      4-bit register              : 2
# Adders/Subtractors               : 6
#      10-bit adder                : 1
#      8-bit subtractor            : 5

Cell Usage :
# BELS                             : 270
#      GND                         : 1
#      LUT1                        : 67
#      LUT1_L                      : 1
#      LUT2                        : 10
#      LUT2_D                      : 1
#      LUT2_L                      : 10
#      LUT3                        : 9
#      LUT3_D                      : 1
#      LUT4                        : 47
#      LUT4_D                      : 5
#      LUT4_L                      : 1
#      MUXCY                       : 56
#      VCC                         : 1
#      XORCY                       : 60
# FlipFlops/Latches                : 78
#      FDC                         : 1
#      FDCE                        : 36
#      FDE                         : 5
#      FDP                         : 3
#      FDPE                        : 9
#      FDR                         : 24
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 31
#      IBUF                        : 9
#      OBUF                        : 22
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-6 

 Number of Slices:                      98  out of   1200     8%  
 Number of Slice Flip Flops:            78  out of   2400     3%  
 Number of 4 input LUTs:               152  out of   2400     6%  
 Number of bonded IOBs:                 31  out of    144    21%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 36    |
XLXI_14_clk:Q                      | NONE                   | 42    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.902ns (Maximum Frequency: 112.334MHz)
   Minimum input arrival time before clock: 8.196ns
   Maximum output required time after clock: 13.367ns
   Maximum combinational path delay: 11.762ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               8.902ns (Levels of Logic = 3)
  Source:            XLXI_14_counter_14 (FF)
  Destination:       XLXI_14_counter_22 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_14_counter_14 to XLXI_14_counter_22
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  XLXI_14_counter_14 (XLXI_14_counter_14)
     LUT4:I0->O            1   0.549   1.035  XLXI_14__n000174 (CHOICE544)
     LUT3_D:I0->O          1   0.549   1.035  XLXI_14__n000198_SW0 (N8582)
     LUT4:I3->O           12   0.549   2.160  XLXI_14__n000198_1 (XLXI_14__n000198_1)
     FDR:R                     0.734          XLXI_14_counter_9
    ----------------------------------------
    Total                      8.902ns (3.466ns logic, 5.436ns route)
                                       (38.9% logic, 61.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_14_clk:Q'
Delay:               7.833ns (Levels of Logic = 3)
  Source:            XLXI_11_num1_9 (FF)
  Destination:       XLXI_11_num1_4 (FF)
  Source Clock:      XLXI_14_clk:Q rising
  Destination Clock: XLXI_14_clk:Q rising

  Data Path: XLXI_11_num1_9 to XLXI_11_num1_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   1.085   1.206  XLXI_11_num1_9 (XLXI_11_num1_9)
     LUT4:I0->O            2   0.549   1.206  XLXI_11__n000919 (CHOICE603)
     LUT4:I2->O           10   0.549   1.980  XLXI_11__n00301 (XLXI_11__n0030)
     LUT2_L:I0->LO         1   0.549   0.000  XLXI_11__n0006<6>1 (XLXI_11__n0006<6>)
     FDCE:D                    0.709          XLXI_11_num1_6
    ----------------------------------------
    Total                      7.833ns (3.441ns logic, 4.392ns route)
                                       (43.9% logic, 56.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              8.196ns (Levels of Logic = 4)
  Source:            qd<5> (PAD)
  Destination:       XLXI_16_Q (FF)
  Destination Clock: clk rising

  Data Path: qd<5> to XLXI_16_Q
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.776   1.440  qd_5_IBUF (qd_5_IBUF)
     LUT2:I0->O            2   0.549   1.206  XLXI_16_Ker29261 (XLXI_16_N2928)
     LUT4:I2->O            2   0.549   1.206  XLXI_16__n0005<2> (XLXI_16__n0005<2>)
     LUT4:I0->O            1   0.549   1.035  XLXI_16__n0004148 (CHOICE511)
     FDCE:CE                   0.886          XLXI_16_Q
    ----------------------------------------
    Total                      8.196ns (3.309ns logic, 4.887ns route)
                                       (40.4% logic, 59.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_14_clk:Q'
Offset:              13.367ns (Levels of Logic = 4)
  Source:            XLXI_11_num_1 (FF)
  Destination:       time2<6> (PAD)
  Source Clock:      XLXI_14_clk:Q rising

  Data Path: XLXI_11_num_1 to time2<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             8   1.085   1.845  XLXI_11_num_1 (XLXI_11_num_1)
     LUT2_D:I0->O          3   0.549   1.332  XLXI_11_Ker39251 (XLXI_11_N3927)
     LUT4:I3->O            7   0.549   1.755  XLXI_11_t2<0>1 (XLXN_21<0>)
     LUT4:I0->O            1   0.549   1.035  XLXI_13_Mrom_ooo_inst_lut4_01 (time2_0_OBUF)
     OBUF:I->O                 4.668          time2_0_OBUF (time2<0>)
    ----------------------------------------
    Total                     13.367ns (7.400ns logic, 5.967ns route)
                                       (55.4% logic, 44.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              9.092ns (Levels of Logic = 2)
  Source:            XLXI_16_qz_0 (FF)
  Destination:       xuanshou<6> (PAD)
  Source Clock:      clk rising

  Data Path: XLXI_16_qz_0 to xuanshou<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             7   1.085   1.755  XLXI_16_qz_0 (XLXI_16_qz_0)
     LUT4:I0->O            1   0.549   1.035  XLXI_5_Mrom_ooo_inst_lut4_01 (xuanshou_0_OBUF)
     OBUF:I->O                 4.668          xuanshou_0_OBUF (xuanshou<0>)
    ----------------------------------------
    Total                      9.092ns (6.302ns logic, 2.790ns route)
                                       (69.3% logic, 30.7% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               11.762ns (Levels of Logic = 4)
  Source:            en (PAD)
  Destination:       time2<6> (PAD)

  Data Path: en to time2<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            15   0.776   2.430  en_IBUF (en_IBUF)
     LUT3:I0->O            7   0.549   1.755  XLXI_11_t2<2>1 (XLXN_21<2>)
     LUT4:I2->O            1   0.549   1.035  XLXI_13_Mrom_ooo_inst_lut4_01 (time2_0_OBUF)
     OBUF:I->O                 4.668          time2_0_OBUF (time2<0>)
    ----------------------------------------
    Total                     11.762ns (6.542ns logic, 5.220ns route)
                                       (55.6% logic, 44.4% route)

=========================================================================
CPU : 9.19 / 11.81 s | Elapsed : 9.00 / 11.00 s
 
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Total memory usage is 60980 kilobytes