top.syr

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Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : top.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : top
Output Format                      : NGC
Target Device                      : xc2s100-6-pq208

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/xilinx仿真/TOP/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file D:/xilinx仿真/TOP/bjq.vhdl in Library work.
Architecture behavioral of Entity bjq is up to date.
Compiling vhdl file D:/xilinx仿真/TOP/dsq.vhdl in Library work.
Architecture behavioral of Entity dsq is up to date.
Compiling vhdl file D:/xilinx仿真/TOP/fpq.vhdl in Library work.
Architecture behavioral of Entity fpq is up to date.
Compiling vhdl file D:/xilinx仿真/TOP/qdq.vhdl in Library work.
Architecture behavioral of Entity qdq is up to date.
Compiling vhdl file D:/xilinx仿真/TOP/top.vhf in Library work.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <bjq> (Architecture <behavioral>).
Entity <bjq> analyzed. Unit <bjq> generated.

Analyzing Entity <dsq> (Architecture <behavioral>).
Entity <dsq> analyzed. Unit <dsq> generated.

Analyzing Entity <fpq> (Architecture <behavioral>).
Entity <fpq> analyzed. Unit <fpq> generated.

Analyzing Entity <qdq> (Architecture <behavioral>).
Entity <qdq> analyzed. Unit <qdq> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <qdq>.
    Related source file is D:/xilinx仿真/TOP/qdq.vhdl.
    Found 1-bit register for signal <q1>.
    Found 4-bit register for signal <qz>.
    Found 1-bit register for signal <G1>.
    Found 1-bit register for signal <Q>.
    Found 4-bit register for signal <Y_s>.
    Summary:
	inferred  11 D-type flip-flop(s).
Unit <qdq> synthesized.


Synthesizing Unit <fpq>.
    Related source file is D:/xilinx仿真/TOP/fpq.vhdl.
    Found 1-bit register for signal <clk>.
    Found 24-bit up counter for signal <counter>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <fpq> synthesized.


Synthesizing Unit <dsq>.
    Related source file is D:/xilinx仿真/TOP/dsq.vhdl.
    Found 10-bit adder for signal <$n0029> created at line 38.
    Found 4-bit down counter for signal <num>.
    Found 10-bit register for signal <num1>.
    Found 1-bit register for signal <q0>.
    Summary:
	inferred   1 Counter(s).
	inferred  11 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <dsq> synthesized.


Synthesizing Unit <bjq>.
    Related source file is D:/xilinx仿真/TOP/bjq.vhdl.
    Found 1-bit register for signal <bout1>.
    Found 1-bit register for signal <bout2>.
    Found 1-bit register for signal <bout3>.
    Found 8-bit down counter for signal <num1>.
    Found 8-bit down counter for signal <num2>.
    Found 8-bit down counter for signal <num3>.
    Summary:
	inferred   3 Counter(s).
	inferred   3 D-type flip-flop(s).
Unit <bjq> synthesized.


Synthesizing Unit <ymq>.
    Related source file is D:/xilinx仿真/TOP/ymq.vhdl.
    Found 16x7-bit ROM for signal <ooo>.
    Summary:
	inferred   1 ROM(s).
Unit <ymq> synthesized.


Synthesizing Unit <top>.
    Related source file is D:/xilinx仿真/TOP/top.vhf.
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 3
 16x7-bit ROM                      : 3
# Adders/Subtractors               : 1
 10-bit adder                      : 1
# Counters                         : 5
 24-bit up counter                 : 1
 8-bit down counter                : 3
 4-bit down counter                : 1
# Registers                        : 11
 1-bit register                    : 8
 10-bit register                   : 1
 4-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...

Optimizing unit <qdq> ...

Optimizing unit <fpq> ...