pic168xa.h

带有LCD

static volatile bit	RX9D	@ (unsigned)&RCSTA*8+0;

/*	CCP2CON bits	*/
static volatile bit	CCP2X	@ (unsigned)&CCP2CON*8+5;
static volatile bit	CCP2Y	@ (unsigned)&CCP2CON*8+4;
static volatile bit	CCP2M3	@ (unsigned)&CCP2CON*8+3;
static volatile bit	CCP2M2	@ (unsigned)&CCP2CON*8+2;
static volatile bit	CCP2M1	@ (unsigned)&CCP2CON*8+1;
static volatile bit	CCP2M0	@ (unsigned)&CCP2CON*8+0;

/*	 ADCON0 bits	*/
static volatile bit	ADCS1	@ (unsigned)&ADCON0*8+7;
static volatile bit	ADCS0 	@ (unsigned)&ADCON0*8+6;
static volatile bit	CHS2	@ (unsigned)&ADCON0*8+5;
static volatile bit	CHS1	@ (unsigned)&ADCON0*8+4;
static volatile bit	CHS0	@ (unsigned)&ADCON0*8+3;
static volatile bit	ADGO	@ (unsigned)&ADCON0*8+2;
static volatile bit	ADON	@ (unsigned)&ADCON0*8+0;

/* 	OPTION bits	*/
static bank1 bit	RBPU	@ (unsigned)&OPTION*8+7;
static bank1 bit	INTEDG	@ (unsigned)&OPTION*8+6;
static bank1 bit	T0CS	@ (unsigned)&OPTION*8+5;
static bank1 bit	T0SE	@ (unsigned)&OPTION*8+4;
static bank1 bit	PSA	@ (unsigned)&OPTION*8+3;
static bank1 bit	PS2	@ (unsigned)&OPTION*8+2;
static bank1 bit	PS1	@ (unsigned)&OPTION*8+1;
static bank1 bit	PS0	@ (unsigned)&OPTION*8+0;

/*      TRISA bits      */
static volatile bank1 bit	TRISA5	@ (unsigned)&TRISA*8+5;
static volatile bank1 bit	TRISA4	@ (unsigned)&TRISA*8+4;
static volatile bank1 bit	TRISA3	@ (unsigned)&TRISA*8+3;
static volatile bank1 bit	TRISA2	@ (unsigned)&TRISA*8+2;
static volatile bank1 bit	TRISA1	@ (unsigned)&TRISA*8+1;
static volatile bank1 bit	TRISA0	@ (unsigned)&TRISA*8+0;

/*      TRISB bits      */
static volatile bank1 bit	TRISB7	@ (unsigned)&TRISB*8+7;
static volatile bank1 bit	TRISB6	@ (unsigned)&TRISB*8+6;
static volatile bank1 bit	TRISB5	@ (unsigned)&TRISB*8+5;
static volatile bank1 bit	TRISB4	@ (unsigned)&TRISB*8+4;
static volatile bank1 bit	TRISB3	@ (unsigned)&TRISB*8+3;
static volatile bank1 bit	TRISB2	@ (unsigned)&TRISB*8+2;
static volatile bank1 bit	TRISB1	@ (unsigned)&TRISB*8+1;
static volatile bank1 bit	TRISB0	@ (unsigned)&TRISB*8+0;

/*      TRISC bits      */
static volatile bank1 bit	TRISC7	@ (unsigned)&TRISC*8+7;
static volatile bank1 bit	TRISC6	@ (unsigned)&TRISC*8+6;
static volatile bank1 bit	TRISC5	@ (unsigned)&TRISC*8+5;
static volatile bank1 bit	TRISC4	@ (unsigned)&TRISC*8+4;
static volatile bank1 bit	TRISC3	@ (unsigned)&TRISC*8+3;
static volatile bank1 bit	TRISC2	@ (unsigned)&TRISC*8+2;
static volatile bank1 bit	TRISC1	@ (unsigned)&TRISC*8+1;
static volatile bank1 bit	TRISC0	@ (unsigned)&TRISC*8+0;

#ifdef	__PINS_40
/*      TRISD bits      */
static volatile bank1 bit	TRISD7	@ (unsigned)&TRISD*8+7;
static volatile bank1 bit	TRISD6	@ (unsigned)&TRISD*8+6;
static volatile bank1 bit	TRISD5	@ (unsigned)&TRISD*8+5;
static volatile bank1 bit	TRISD4	@ (unsigned)&TRISD*8+4;
static volatile bank1 bit	TRISD3	@ (unsigned)&TRISD*8+3;
static volatile bank1 bit	TRISD2	@ (unsigned)&TRISD*8+2;
static volatile bank1 bit	TRISD1	@ (unsigned)&TRISD*8+1;
static volatile bank1 bit	TRISD0	@ (unsigned)&TRISD*8+0;

/*      TRISE bits      */
static volatile bank1 bit	IBF	@ (unsigned)&TRISE*8+7;
static volatile bank1 bit	OBF	@ (unsigned)&TRISE*8+6;
static volatile bank1 bit	IBOV	@ (unsigned)&TRISE*8+5;
static volatile bank1 bit	PSPMODE	@ (unsigned)&TRISE*8+4;

static volatile bank1 bit	TRISE2  @ (unsigned)&TRISE*8+2;
static volatile bank1 bit	TRISE1  @ (unsigned)&TRISE*8+1;
static volatile bank1 bit	TRISE0  @ (unsigned)&TRISE*8+0;
#endif

/*	PIE1 bits	*/
#ifdef	__PINS_40
static volatile bank1 bit	PSPIE	@ (unsigned)&PIE1*8+7;
#endif
static volatile bank1 bit	ADIE	@ (unsigned)&PIE1*8+6;
static volatile bank1 bit	RCIE	@ (unsigned)&PIE1*8+5;
static volatile bank1 bit	TXIE	@ (unsigned)&PIE1*8+4;
static volatile bank1 bit	SSPIE	@ (unsigned)&PIE1*8+3;
static volatile bank1 bit	CCP1IE	@ (unsigned)&PIE1*8+2;
static volatile bank1 bit	TMR2IE	@ (unsigned)&PIE1*8+1;
static volatile bank1 bit	TMR1IE	@ (unsigned)&PIE1*8+0;

/*	PIE2 bits	*/
static volatile bank1 bit	CMIE	@ (unsigned)&PIE2*8+6;
static volatile bank1 bit	EEIE	@ (unsigned)&PIE2*8+4;
static volatile bank1 bit	BCLIE	@ (unsigned)&PIE2*8+3;
static volatile bank1 bit	CCP2IE	@ (unsigned)&PIE2*8+0;

/*	PCON bits	*/
static volatile bank1 bit	POR	@ (unsigned)&PCON*8+1;	
static volatile bank1 bit	BOR	@ (unsigned)&PCON*8+0;	

/*	SSPCON2 bits */
static volatile bank1 bit	GCEN	@ (unsigned)&SSPCON2*8+7;
static volatile bank1 bit	ACKSTAT	@ (unsigned)&SSPCON2*8+6;
static volatile bank1 bit	ACKDT	@ (unsigned)&SSPCON2*8+5;
static volatile bank1 bit	ACKEN	@ (unsigned)&SSPCON2*8+4;
static volatile bank1 bit	RCEN	@ (unsigned)&SSPCON2*8+3;
static volatile bank1 bit	PEN	@ (unsigned)&SSPCON2*8+2;
static volatile bank1 bit	RSEN	@ (unsigned)&SSPCON2*8+1;
static volatile bank1 bit	SEN	@ (unsigned)&SSPCON2*8+0;

/*      SSPSTAT bits    */
static volatile bank1 bit	STAT_SMP	@ (unsigned)&SSPSTAT*8+7;
static volatile bank1 bit	STAT_CKE	@ (unsigned)&SSPSTAT*8+6;
static volatile bank1 bit	STAT_DA		@ (unsigned)&SSPSTAT*8+5;
static volatile bank1 bit	STAT_P		@ (unsigned)&SSPSTAT*8+4;
static volatile bank1 bit	STAT_S		@ (unsigned)&SSPSTAT*8+3;
static volatile bank1 bit	STAT_RW		@ (unsigned)&SSPSTAT*8+2;
static volatile bank1 bit	STAT_UA		@ (unsigned)&SSPSTAT*8+1;
static volatile bank1 bit	STAT_BF		@ (unsigned)&SSPSTAT*8+0;

/*	TXSTA bits	*/
static volatile bank1 bit	CSRC	@ (unsigned)&TXSTA*8+7;
static volatile bank1 bit	TX9	@ (unsigned)&TXSTA*8+6;
static volatile bank1 bit	TXEN	@ (unsigned)&TXSTA*8+5;
static volatile bank1 bit	SYNC	@ (unsigned)&TXSTA*8+4;
static volatile bank1 bit	BRGH	@ (unsigned)&TXSTA*8+2;
static volatile bank1 bit	TRMT	@ (unsigned)&TXSTA*8+1;
static volatile bank1 bit	TX9D	@ (unsigned)&TXSTA*8+0;

/*	CMCON Bits	*/
static volatile bank1 bit	C2OUT	@ (unsigned)&CMCON*8+7;
static volatile bank1 bit	C1OUT	@ (unsigned)&CMCON*8+6;
static volatile bank1 bit	C2INV	@ (unsigned)&CMCON*8+5;
static volatile bank1 bit	C1INV	@ (unsigned)&CMCON*8+4;
static volatile bank1 bit	CIS	@ (unsigned)&CMCON*8+3;
static volatile bank1 bit	CM2	@ (unsigned)&CMCON*8+2;
static volatile bank1 bit	CM1	@ (unsigned)&CMCON*8+1;
static volatile bank1 bit	CM0	@ (unsigned)&CMCON*8+0;

/*	CVRCON Bits	*/
static volatile bank1 bit	CVREN	@ (unsigned)&CVRCON*8+7;
static volatile bank1 bit	CVROE	@ (unsigned)&CVRCON*8+6;
static volatile bank1 bit	CVRR	@ (unsigned)&CVRCON*8+5;
static volatile bank1 bit	CVR3	@ (unsigned)&CVRCON*8+3;
static volatile bank1 bit	CVR2	@ (unsigned)&CVRCON*8+2;
static volatile bank1 bit	CVR1	@ (unsigned)&CVRCON*8+1;
static volatile bank1 bit	CVR0	@ (unsigned)&CVRCON*8+0;

/*	ADCON1 bits	*/
static volatile bank1 bit	ADFM	@ (unsigned)&ADCON1*8+7;
static volatile bank1 bit	ADCS2	@ (unsigned)&ADCON1*8+6;
static volatile bank1 bit	PCFG3	@ (unsigned)&ADCON1*8+3;
static volatile bank1 bit	PCFG2	@ (unsigned)&ADCON1*8+2;
static volatile bank1 bit	PCFG1	@ (unsigned)&ADCON1*8+1;
static volatile bank1 bit	PCFG0	@ (unsigned)&ADCON1*8+0;

/*	EECON1 bits */
static volatile bank3 bit	EEPGD	@ (unsigned)&EECON1*8+7;
static volatile bank3 bit	WRERR	@ (unsigned)&EECON1*8+3;
static volatile bank3 bit	WREN	@ (unsigned)&EECON1*8+2;
static volatile bank3 bit	WR	@ (unsigned)&EECON1*8+1;
static volatile bank3 bit	RD	@ (unsigned)&EECON1*8+0;


#define CONFIG_ADDR	0x2007

/*osc configurations*/
#define RC		0x3FFF	// resistor/capacitor
#define HS		0x3FFE	// high speed crystal/resonator
#define XT		0x3FFD	// crystal/resonator
#define LP		0x3FFC	// low power crystal/resonator

/*watchdog*/
#define WDTEN		0x3FFF	// enable watchdog timer
#define WDTDIS		0x3FFB	// disable watchdog timer

/*power up timer*/
#define PWRTEN		0x3FF7	// enable power up timer
#define PWRTDIS		0x3FFF	// disable power up timer

/*brown out reset*/
#define BOREN		0x3FFF	// enable brown out reset
#define BORDIS		0x3FBF	// disable brown out reset

/*Low Voltage Programmable*/
#define LVPEN		0x3FFF	// low voltage programming enabled
#define LVPDIS		0x3F7F	// low voltage programming disabled

/*data code protected*/
#define DP		0x3EFF	// protect data code
// alternately
#define DPROT		0x3EFF	// use DP
#define DUNPROT		0x3FFF	// use UNPROTECT

/* Flash memory write enable/protect */
#define WRTEN		0x3FFF	/* flash memory write enabled */
#define WP1		0x3DFF  /* protect 0000 - 00FF */
#define WP2		0x3BFF  /* protect 0000 - 07FF(76A/77A) / 03FF(73A/74A) */
#define WP3		0x39FF  /* protect 0000 - 1FFF(76A/77A) / 0FFF(73A/74A) */

/*debug option*/
#define DEBUGEN		0x37FF	// debugger enabled
#define DEBUGDIS	0x3FFF	// debugger disabled

/*code protection*/
#define PROTECT		0x1FFF	/* protect program code */
#define UNPROTECT	0x3FFF	/* do not protect the code */