jg_f33.vhd

来自「任意整数分频」· VHDL 代码 · 共 38 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--test JG_F33
--use UNISIM.VComponents.all;
entity JG_F33 is
    Port ( CLK_IN : in std_logic;
           REST_IN : in std_logic;
           DIV_OUT_33 : out std_logic);
end JG_F33;

architecture Behavioral of JG_F33 is

begin

	process(CLK_IN,REST_IN)
	variable		v_int_temp	:	integer range 0 to 40:=0;
	begin
		if(REST_IN='0')then
	   DIV_OUT_33<='1';
		v_int_temp:=0;
	   elsif(CLK_IN'event and CLK_IN='1')then
	   	v_int_temp:=v_int_temp+1;
			if(v_int_temp<=3)	then DIV_OUT_33<='1';
			elsif (v_int_temp=31) then  v_int_temp:=0; DIV_OUT_33<='1';
			else  DIV_OUT_33<='0';
			end if;
	   end if;
	end process;


end Behavioral;