wrsbcarm7.h

一个基于三星ARM7系列的S3C44B0 的vxWorks的BSP源文件包。

#define CasPrechargeTime0  1             /*(Tcp)0=1cycle,1=2cycle*/
#define CasStrobeTime0     1             /*(Tcs)0=1cycle ~ 3=4cycle*/
#define DRAMCON0Reserved   1             /* Must be set to 1*/
#define RAS2CASDelay0      0             /*(Trc)0=1cycle,1=2cycle*/
#define RASPrechargeTime0  1             /*(Trp)0=1cycle ~ 3=4clcyle*/
#define DRAMBasePtr0       (0x100<<10)   /*=0x1000000 */
#define DRAMBasePtr0_S     0x00          /* now RAM moved to zero */


#define DRAMEndPtr0        (((LOCAL_MEM_SIZE >> 16) + 0x100) << 20)  /*=0x00800000 - 8 MB */
#define DRAMEndPtr0_S      ((LOCAL_MEM_SIZE >> 16) << 20)  /*=0x00800000 - 8 MB */

#define NoColumnAddr0      2             /*0=8bit,1=9bit,2=10bit,3=11bits*/

#define Tcs0           (CasStrobeTime0<<1)
#define Tcp0           (CasPrechargeTime0<<3)
#define dumy0          (DRAMCON0Reserved<<4)        /*dummy cycle*/
#define Trc0           (RAS2CASDelay0<<7)
#define Trp0           (RASPrechargeTime0<<8)
#define CAN0           (NoColumnAddr0<<30)

#define rDRAMCON0      (CAN0+DRAMEndPtr0+DRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0)
#define rDRAMCON0_S    (CAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0)

/****************************************************************************
 * -> DRAMCONx : unused RAM Banks
 */
#define rDRAMCON1         0x00
#define rDRAMCON2         0x00
#define rDRAMCON3         0x00

/****************************************************************************
 * -> DRAMCON0 : RAM Bank0 control register (for SDRAM)
 */
#define B6_MT		0x3
#define B6_Trcd		0x0
#define B6_SCAN		0x0
#define rSDRAMCON0  ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))

/****************************************************************************
 * -> DRAMCONx : unused SYNC DRAM Banks
 */
#define B7_MT		0x3
#define B7_Trcd		0x0
#define B7_SCAN		0x0
#define rSDRAMCON1  ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))


/**************************************************************************
 * -> REFEXTCON : External I/O & Memory Refresh cycle Control Register 
 */

#define REFEN		0x1	
#define TREFMD		0x0	
#define Trp			0x0	
#define Trc			0x1	
#define Tchr		0x2	
#define REFCNT		1050

#define rREFEXTCON 	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)

#define rBANKSIZE	0x10
#define rMRSRB6		0x20
#define rMRSRB7		0x20

/******************************************************************
 *SRefCycle EQU 16 ;Unit [us], 4k refresh 64ms
 */

#define SRefCycle          8         /*Unit [us], 4k refresh 64ms*/
#define ROWcycleTime       3         /*0=1cycle, 1=2cycle, 2=3cycle,
                                       3=4cycle, 4=5cycle,*/
#define SRefCycleValue     ((2048+1-(SRefCycle*fMCLK))<<21)
#define STrc               (ROWcycleTime<<17)
#define rSREFEXTCON        (SRefCycleValue+STrc+ExtIOBase)

#if 1
/* interrupt levels */
#define INT_LVL_EXTINT0        25    /* External Interrupt0 */
#define INT_LVL_EXTINT1        24    /* External Interrupt1 */
#define INT_LVL_EXTINT2        23    /* External Interrupt2 */
#define INT_LVL_EXTINT3        22    /* External Interrupt3 */
#define INT_LVL_EXTINT4567	   21
#define INT_LVL_TICK		   20
#define INT_LVL_ZDMA0          19
#define INT_LVL_ZDMA1          18
#define INT_LVL_BDMA0		   17
#define INT_LVL_BDMA1          16
#define INT_LVL_WDT			   15
#define INT_LVL_UERR		   14
#define INT_LVL_TIMER0		   13
#define INT_LVL_TIMER1		   12
#define INT_LVL_TIMER2		   11
#define INT_LVL_TIMER3		   10
#define INT_LVL_TIMER4		   9
#define INT_LVL_TIMER5		   8
#define INT_LVL_UARTRX0		   7
#define INT_LVL_UARTRX1		   6
#define	INT_LVL_IIC			   5
#define INT_LVL_SIO			   4
#define INT_LVL_UARTTX0        3    /* UART 0 Transmit Interrupt */
#define INT_LVL_UARTTX1        2    /* UART 1 Transmit Interrupt */
#define INT_LVL_RTC		       1    /* UART 1 Receive & Error Interrupt */
#define INT_LVL_ADC			   0    /* GDMA channel 0 interrupt*/
#else
#define INT_LVL_EXTINT0        0    /* External Interrupt0 */
#define INT_LVL_EXTINT1        1    /* External Interrupt1 */
#define INT_LVL_EXTINT2        2    /* External Interrupt2 */
#define INT_LVL_EXTINT3        3    /* External Interrupt3 */
#define INT_LVL_EXTINT4567	   4
#define INT_LVL_TICK		   5
#define INT_LVL_ZDMA0          6
#define INT_LVL_ZDMA1          7
#define INT_LVL_BDMA0		   8
#define INT_LVL_BDMA1          9
#define INT_LVL_WDT			   10
#define INT_LVL_UERR		   11
#define INT_LVL_TIMER0		   12
#define INT_LVL_TIMER1		   13
#define INT_LVL_TIMER2		   14
#define INT_LVL_TIMER3		   15
#define INT_LVL_TIMER4		   16
#define INT_LVL_TIMER5		   17
#define INT_LVL_UARTRX0		   18
#define INT_LVL_UARTRX1		   19
#define	INT_LVL_IIC			   20
#define INT_LVL_SIO			   21
#define INT_LVL_UARTTX0        22    /* UART 0 Transmit Interrupt */
#define INT_LVL_UARTTX1        23    /* UART 1 Transmit Interrupt */
#define INT_LVL_RTC		       24    /* UART 1 Receive & Error Interrupt */
#define INT_LVL_ADC			   25    /* GDMA channel 0 interrupt*/
#endif
/* interrupt vectors */

#define INT_VEC_EXTINT0         IVEC_TO_INUM(INT_LVL_EXTINT0)  
#define INT_VEC_EXTINT1         IVEC_TO_INUM(INT_LVL_EXTINT1)  
#define INT_VEC_EXTINT2         IVEC_TO_INUM(INT_LVL_EXTINT2)  
#define INT_VEC_EXTINT3         IVEC_TO_INUM(INT_LVL_EXTINT3)  
#define INT_VEC_EXTINT4567	    IVEC_TO_INUM(INT_LVL_EXTINT4567)  
#define INT_VEC_TICK		    IVEC_TO_INUM(INT_LVL_TICK)  
#define INT_VEC_ZDMA0           IVEC_TO_INUM(INT_LVL_ZDMA0)  
#define INT_VEC_ZDMA1           IVEC_TO_INUM(INT_LVL_ZDMA1)  
#define INT_VEC_BDMA0		    IVEC_TO_INUM(INT_LVL_BDMA0)    
#define INT_VEC_BDMA1           IVEC_TO_INUM(INT_LVL_BDMA1)    
#define INT_VEC_WDT			    IVEC_TO_INUM(INT_LVL_WDT)   
#define INT_VEC_UERR		    IVEC_TO_INUM(INT_LVL_UERR)   
#define INT_VEC_TIMER0		    IVEC_TO_INUM(INT_LVL_TIMER0)  
#define INT_VEC_TIMER1		    IVEC_TO_INUM(INT_LVL_TIMER1)  
#define INT_VEC_TIMER2		    IVEC_TO_INUM(INT_LVL_TIMER2)  
#define INT_VEC_TIMER3		    IVEC_TO_INUM(INT_LVL_TIMER3)  
#define INT_VEC_TIMER4		    IVEC_TO_INUM(INT_LVL_TIMER4)   
#define INT_VEC_TIMER5		    IVEC_TO_INUM(INT_LVL_TIMER5)   
#define INT_VEC_UARTRX0		    IVEC_TO_INUM(INT_LVL_UARTRX0)    
#define INT_VEC_UARTRX1		    IVEC_TO_INUM(INT_LVL_UARTRX1)    
#define INT_VEC_IIC			    IVEC_TO_INUM(INT_LVL_IIC)      
#define INT_VEC_SIO				IVEC_TO_INUM(INT_LVL_SIO) 
#define INT_VEC_UARTTX0     	IVEC_TO_INUM(INT_LVL_UARTTX0) 
#define INT_VEC_UARTTX1     	IVEC_TO_INUM(INT_LVL_UARTTX1)
#define INT_VEC_RTC		    	IVEC_TO_INUM(INT_LVL_RTC)
#define INT_VEC_ADC				IVEC_TO_INUM(INT_LVL_ADC)    
                      
                      
                       
                       
/**********************************************************************************************************
 * Cache Definitions   
 *                     
 */

#define NON_CACHE_REGION    0x4000000
#define SBCARM7_CACHE_ENABLE    0x02
#define SBCARM7_CACHE_4K        0x00
#define SBCARM7_CACHE_8K        0x10
#define SBCARM7_CACHE_MODE      0x30
#define SBCARM7_WRITE_BUFF      0x04
#define SBCARM7_TAGRAM          0x11000000


/*
 *
 * definitions for the SBCARM7 Timer:
 * two timers clocked from same source and with the same reload overhead
 */

#define SYS_TIMER_CLK               (SBCARM7_CPU_SPEED)    /* Frequency of counter/timer */
#define AUX_TIMER_CLK               (SBCARM7_CPU_SPEED)    /* Frequency of counter/timer */

#define SBCARM7_RELOAD_TICKS            3        /* three ticks to reload timer */

#define SYS_TIMER_CLEAR(x)          (SBCARM7_TIMER_T1CLEAR(x))    /* sys Clk is timer 1  */
#define SYS_TIMER_CTRL(x)           (SBCARM7_TIMER_T1CTRL(x))
#define SYS_TIMER_LOAD(x)           (SBCARM7_TIMER_T1LOAD(x))
#define SYS_TIMER_VALUE(x)          (SBCARM7_TIMER_T1VALUE(x))
#define SBCARM7_TIMER_VALUE_MASK        0xFFFF
#define AUX_TIMER_CLEAR(x)          (SBCARM7_TIMER_T2CLEAR(x))    /* aux Clk is timer 2  */
#define AUX_TIMER_CTRL(x)           (SBCARM7_TIMER_T2CTRL(x))
#define AUX_TIMER_LOAD(x)           (SBCARM7_TIMER_T2LOAD(x))
#define AUX_TIMER_VALUE(x)          (SBCARM7_TIMER_T2VALUE(x))

#define SYS_TIMER_INT_LVL           (INT_LVL_TIMER5)
#define AUX_TIMER_INT_LVL           (INT_LVL_TIMER4)

/******************************************************************************************
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * Note that it takes 3 ticks to reload the 16-bit counter and we don't
 * accept values that would mean a zero reload value as we don't know what
 * that will do.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value+3))
 * max frequency = rounddown(clock_rate/(min_counter_value+3))
 * i.e.              SYS_CLK_RATE_MAX (SYS_TIMER_CLK/4)
 * However, we must set maxima that are sustainable on a running
 * system. Experiments suggest that a 16MHz PID board can sustain a
 * maximum clock rate of 10000 to 10500. The values below have been
 * chosen so that there is a reasonable margin and the BSP passes the
 * test suite.
 */

#define SYS_CLK_RATE_MIN      10
#define SYS_CLK_RATE_MAX      10000
#define AUX_CLK_RATE_MIN      2
#define AUX_CLK_RATE_MAX      10000
#define SBCARM7_RESET_RAM_BASE    0xc000000  RAM base in reset memory map */ 

/*
 * Our MAC address definition.  User can change this value as
 * per requirement.  Note, the least significant byte of the
 * address is changed to the value of the user DIP switch setting.
 * SW4-D0 is the least significant bit of this byte.  Open=0.
 */

#define ETHERNET_MAC_ADRS { 0x00, 0xA0, 0x88, 0x88, 0x88, 0x00 }

#ifdef __cplusplus
}
#endif

#endif    /* INCsbcarm7h */