wrsbcarm7.h

一个基于三星ARM7系列的S3C44B0 的vxWorks的BSP源文件包。

/************************************************
 * modify 	: hugang [e-mail]			*
 * data		: 2004-05-06						*
 ************************************************/

/* sbcarm7.h - WindRiver SBC ARM7 header file */


/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01f,16jul02,m_h  C++ protection
01e,04jan02,m_h  minor cleanup
01d,03dec01,m_h  remove Diab warnings
01c,27sep01,m_h  base MAC address on user DIP setting
01b,22may01,m_h  documentation
01a,12apr01,m_h  created from snds100 template.
*/

/*
This file contains I/O address and related constants for the SBC ARM7 board.
*/

#ifndef    INCsbcarm7h
#define    INCsbcarm7h

#ifdef __cplusplus
extern "C" {
#endif

#include "sngks32c.h"


#define TARGET_SBCARM7


#define SBCARM7_FLASH_BASE 0x00000000


/*
 * Local-to-Bus memory address constants:
 * the local memory address always appears at 0 locally;
 * it is not dual ported.
 */

#define LOCAL_MEM_LOCAL_ADRS  0x0c000000    /* fixed */
#define LOCAL_MEM_BUS_ADRS    0x0c000000    /* fixed */


#define BUS                   BUS_TYPE_NONE


#define SBCARM7_CPU_SPEED         60000000    /* CPU clocked at 50 MHz. The timer */
                    /* speed is related to this */


/* definitions for the KS32C50100 UART */

#define N_SBCARM7_UART_CHANNELS     2        /* number of SBCARM7 UART chans */
#define N_SIO_CHANNELS          N_SBCARM7_UART_CHANNELS
#define N_UART_CHANNELS         N_SBCARM7_UART_CHANNELS
#define UART_REG_ADDR_INTERVAL  1        /* registers 4 bytes apart */


/* LED Registers (write) */
#define  SBCARM7_LEDREG             0x3fd4000

/* USER DIP switch (read) */
#define  SBCARM7_USERREG            0x3fd4000
#define READ_USERDIP()              (*((volatile char *)SBCARM7_USERREG) & 0xff)

/*************************************************************************
 *
 * DRAM Memory Bank 0 area MAP for Exception vector table 
 * and Stack, User code area. 
 *
 */

#define DRAM_BASE           0x0          /* Final start address of DRAM */
#define DRAM_LIMIT          0x400000
#define RESET_DRAM_START    0xc000000    /* Start of DRAM on power-up */
#define RESET_ROM_START     0x0          /* Start of ROM on power-up */

/****************************************************************************
 *
 * Format of the Program Status Register 
 */

#define FBit         0x40
#define IBit         0x80
#define LOCKOUT      0xC0     /* Interrupt lockout value */
#define LOCK_MSK     0xC0     /* Interrupt lockout mask value */
#define MODE_MASK    0x1F     /* Processor Mode Mask */
#define UDF_MODE     0x1B     /* Undefine Mode(UDF) */
#define ABT_MODE     0x17     /* Abort Mode(ABT) */
#define SUP_MODE     0x13     /* Supervisor Mode (SVC) */
#define IRQ_MODE     0x12     /* Interrupt Mode (IRQ) */
#define FIQ_MODE     0x11     /* Fast Interrupt Mode (FIQ) */
#define USR_MODE     0x10     /* User Mode(USR) */

/*************************************************************************
 * SYSTEM CLOCK 
 */

#define MHz            1000000
#define fMCLK_MHz      60000000     /* 50MHz, KS32C50100*/
#define fMCLK          60           /* fMCLK_MHz/MHz */

/*************************************************************************
 * SYSTEM MEMORY CONTROL REGISTER EQU TABLES 
 */

/* SYSCFG Register Value */
#define SYSCONFIG_VAL           0x07ffffa0    /* System Configuration Value, EDO RAM */
#define SYSCONFIG_VAL_SDRAM     0x87ffffa0    /* System Configuration Value, SDRAM */

#define M_DIV	52
#define P_DIV	2
#define S_DIV	1

#define	rCLKCON	   		0x7ff8
#define	rPLLCON	   		((M_DIV<<12)+(P_DIV<<4)+S_DIV)
#define	rLOCKTIME  		0xfff

#define S3C_EXC_BASE    0x0c000100

/* EXTACONx External I/O access timing register Values */
#define tCOS0           (1<<0)
#define tACS0           (1<<3)
#define tCOH0           (1<<6)
#define tACC0           (1<<9)
#define tCOS1           (1<<16)
#define tACS1           (1<<19)
#define tCOH1           (1<<22)
#define tACC1           (1<<25)

#define rEXTACON0    (tCOS0+tACS0+tCOH0+tACC0+tCOS1+tACS1+tCOH1+tACC1)

#define tCOS2           (7<<0)
#define tACS2           (7<<3)
#define tCOH2           (7<<6)
#define tACC2           (7<<9)
#define tCOS3           (7<<16)
#define tACS3           (7<<19)
#define tCOH3           (7<<22)
#define tACC3           (7<<25)

#define rEXTACON1    (tCOS2+tACS2+tCOH2+tACC2+tCOS3+tACS3+tCOH3+tACC3)

/***********************************************************
 *
 * -> EXTDBWTH : Memory Bus Width register
 */


#define	rEXTDBWTH	0x11111001    

/***********************************************************
 *
 * -> ROMCON0 : ROM Bank0 Control register 
 */

#define	B0_Tacs		0x0
#define	B0_Tcos		0x0	
#define	B0_Tacc		0x6	
#define	B0_Tcoh		0x0
#define	B0_Tah		0x0	
#define	B0_Tacp		0x0
#define	B0_PMC		0x0
#define rROMCON0    ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))


/***************************************************************************
 * -> ROMCON1 : ROM Bank1 Control register, Mailbox Interface
 */

#define	B1_Tacs		0x3	
#define	B1_Tcos		0x3	
#define	B1_Tacc		0x7	
#define	B1_Tcoh		0x3	
#define	B1_Tah		0x3
#define	B1_Tacp		0x3	
#define	B1_PMC		0x0	
#define rROMCON1    ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))

/***************************************************************************
 * -> ROMCON2 : ROM Bank2 Control register, EEPROM
 */

#define	B2_Tacs		0x3	
#define	B2_Tcos		0x3	
#define	B2_Tacc		0x7	
#define	B2_Tcoh		0x3	
#define	B2_Tah		0x3	
#define	B2_Tacp		0x3	
#define	B2_PMC		0x0	
#define rROMCON2        ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))

/***************************************************************************
 * -> ROMCONx : unused ROM Bank Control registers
 */

/* Bank 3 parameter */
#define	B3_Tacs		0x3	
#define	B3_Tcos		0x3	
#define	B3_Tacc		0x7	
#define	B3_Tcoh		0x3	
#define	B3_Tah		0x3	
#define	B3_Tacp		0x3	
#define	B3_PMC		0x0	

/* Bank 4 parameter */
#define	B4_Tacs		0x3	
#define	B4_Tcos		0x3	
#define	B4_Tacc		0x7	
#define	B4_Tcoh		0x3	
#define	B4_Tah		0x3	
#define	B4_Tacp		0x3	
#define	B4_PMC		0x0	

/* Bank 5 parameter */
#define	B5_Tacs		0x3	
#define	B5_Tcos		0x3	
#define	B5_Tacc		0x7	
#define	B5_Tcoh		0x3	
#define	B5_Tah		0x3	
#define	B5_Tacp		0x3	
#define	B5_PMC		0x0	

#define rROMCON3	((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
#define rROMCON4	((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
#define rROMCON5	((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))

/****************************************************************************
 * -> DRAMCON0 : RAM Bank0 control register  (EDO)
 */
#define EDO_Mode0          1             /*(EDO)0=Normal, 1=EDO DRAM*/