rominit.s

（1）本人基于MPC860的vxworks bsp的程序 （2）实现了FEC 100M和 SCC 10M的网口功能 （3）实现了nor flash的TFFS文件系统 （4）实现了系统的自检 （

/* romInit.s - Motorola 860ads ROM initialization module */

/* Copyright 1984-1996 Wind River Systems, Inc. */
	.data
	.globl  copyright_wind_river
	.long   copyright_wind_river

/*
modification history
--------------------
01a,16Mar05,yanyuan  written.

*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"	
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"

/* MPC860T memory control registers bitS definition for specific board. */

/* MAMR default board*/
#define MAMR_DEFAULT_VALUE (MAMR_PTAE | MAMR_AMA_TYPE_2 | 		\
			    MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | 		\
			    MAMR_GPL_A4DIS | MAMR_RLFA_1X | 		\
			    MAMR_WLFA_1X | MAMR_TLFA_4X)
 
#define MBMR_DEFAULT_VALUE (MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | 	\
			    MAMR_G0CLA_A11 | MAMR_RLFA_1X | 		\
			    MAMR_WLFA_1X | MAMR_TLFA_1X)

/* MCR */
/* define the values according to the board configuration. */
#define MCR_UM_MB (MCR_UM_UPMA | MCR_MB_CS1)

#define ADS860_RAMTABLE
#undef MICRON_RAMTABLE

/* internals */

	.globl	_romInit	/* start of system code */
	.globl	romInit		/* start of system code */
	
	/* externals */

	.extern romStart	/* system initialization routine */

	.text
	.align 2

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

*/

_romInit:
romInit:
    bl	cold		/* jump to the cold boot initialization */
	
    bl	start		/* jump to the warm boot initialization */

    /* copyright notice appears at beginning of ROM (in TEXT segment) */

    .ascii   "Copyright 1984-1996 Wind River Systems, Inc."
    .align 2

cold:
    li	r3, BOOT_COLD	/* set cold boot as start type */

    /*
    * When the PowerPC 860 is powered on, the processor fletch the
    * instructions located at the address 0x100. We need to jump
    * from the address 0x100 to the Flash space.
    */

    lis	r4, HIADJ(start)		/* load r4 with the address */
    addi	r4, r4, LO(start)		/* of start */

    lis	r5, HIADJ(romInit)		/* load r5 with the address */
    addi	r5, r5, LO(romInit)		/* of romInit() */

    lis	r6, HIADJ(ROM_TEXT_ADRS)	/* load r6 with the address */
    addi	r6, r6, LO(ROM_TEXT_ADRS)	/* of ROM_TEXT_ADRS */

    sub	r4, r4, r5			
    add	r4, r4, r6 

    mtspr	LR, r4				/* save destination address*/
						/* into LR register */
    blr					/* jump to flash mem address */
			
start:
    /* set the MSR register to a known state */

    xor	r4, r4, r4		/* clear register R4 */
    mtmsr 	r4			/* clear the MSR register */

    /* DER - clear the Debug Enable Register */

    mtspr	DER, r4

    /* ICR - clear the Interrupt Cause Register */

    mtspr	ICR, r4

    /* 
    * ICTRL - initialize the Intstruction Support Control register
    */

    lis	r5, HIADJ(0x00000007)
    addi	r5, r5, LO(0x00000007)
    mtspr	ICTRL, r5

    /* disable the instruction/data cache */
	
    lis	r4, HIADJ ( CACHE_CMD_DISABLE)		/* load disable cmd */
    addi	r4, r4, LO (CACHE_CMD_DISABLE)
    mtspr	IC_CST, r4				/* disable I cache */
    mtspr	DC_CST, r4				/* disable D cache */

    /* unlock the instruction/data cache */

    lis	r4, HIADJ ( CACHE_CMD_UNLOCK_ALL)	/* load unlock cmd */
    addi	r4, r4, LO (CACHE_CMD_UNLOCK_ALL)
    mtspr	IC_CST, r4			/* unlock all I cache lines */
    mtspr	DC_CST, r4			/* unlock all D cache lines */

    /* invalidate the instruction/data cache */

    lis	r4, HIADJ (CACHE_CMD_INVALIDATE)   /* load invalidate cmd*/
    addi	r4, r4, LO (CACHE_CMD_INVALIDATE)
    mtspr	IC_CST, r4		/* invalidate all I cache lines */
    mtspr	DC_CST, r4		/* invalidate all D cache lines */

    /*
    * initialize the IMMR register before any non-core registers
    * modification.
    */

    lis	r4, HIADJ( INTERNAL_MEM_MAP_ADDR)	
    addi	r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
    mtspr	IMMR, r4		/* initialize the IMMR register */

    mfspr	r4, IMMR		/* read it back, to be sure */
    rlwinm  r4, r4, 0, 0, 15	/* only high 16 bits count */

    /* SYPCR - turn off the system protection stuff */
	
    lis	r5, HIADJ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
    addi	r5, r5, LO(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
    stw	r5, SYPCR(0)(r4)

    /*
    * Map the bank 0 to the flash area - On the board at reset time
    * the bank 0 is already used to map the flash.
    */

    lis	r5, HIADJ( (ROM_BASE_ADRS & BR_BA_MSK) | BR_PS_16 | BR_V)
    addi	r5, r5, LO((ROM_BASE_ADRS & BR_BA_MSK) | BR_PS_16 | BR_V)
    stw	r5, BR0(0)(r4)

    lis	r5, HIADJ( 0xff800000 | OR_BI | OR_SCY_13_CLK )
    addi	r5, r5, LO(0xff800000 | OR_BI | OR_SCY_13_CLK )
    stw	r5, OR0(0)(r4)	

    /*
    * Map the bank 2 to the ZL50114.
    */
    lis	r5, HIADJ(0xff000D60)
    addi	r5, r5, LO(0xff000D60)
    stw	r5, OR2(0)(r4)

    lis	r5, HIADJ((WM7040_ZL50114_BASE & BR_BA_MSK) | BR_V)
    addi	r5, r5, LO((WM7040_ZL50114_BASE & BR_BA_MSK) | BR_V)
    stw	r5, BR2(0)(r4)

    /*
    * Map the bank 7 to the DS21455.
    */
    lis	r5, HIADJ(0xffff8DF0)
    addi	r5, r5, LO(0xffff8DF0)
    stw	r5, OR7(0)(r4)   

    lis	r5, HIADJ((WM7040_DS21455_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
    addi	r5, r5, LO((WM7040_DS21455_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
    stw	r5, BR7(0)(r4)

    /*SIUMCR - set the SIUMCR register for important debug port, etc... stuff */

    lis	r5, HIADJ(SIUMCR_DBGC | SIUMCR_DLK)
    addi	r5, r5, LO(SIUMCR_DBGC | SIUMCR_DLK)
    stw	r5, SIUMCR(0)(r4)

    /* TBSCR - initialize the Time Base Status and Control register */


    /* PISCR - set PIT status and control init value */

	
    /* PLPRCR - set the SPLL frequency*/

		lis	r5, HIADJ((0x0000C000|(SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT)))
    addi	r5, r5, LO((0x0000C000|(SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT)))
		stw	r5, PLPRCR(0)(r4)

		/* MPTPR - we program the MPTPR with the largest allowed divider 
	 	* and the PTA value accordingly. So here we figure out the 
	 	* correct value for the PTA field. */
	 	/* divide by 16 */		

		li	r5, MPTPR_PTP_DIV16 
		sth	r5, MPTPR(0)(r4)

		/* initialize MxMR but do not enable refresh until after 
		* SDRAM initialization. */	

		lis     r5, HIADJ (0xD0002111)
		addi    r5, r5, LO (0xD0002111)
		stw     r5, MAMR(0)(r4)   

		/******************************************************************
		*
		* Initialize the Ram Array
		*
		*****************************************************************/
	 
		/*load r6/r7 with the start/end address of the UPM table*/

		lis	r6, HIADJ( upmaTableSdram)
		addi	r6, r6, LO(upmaTableSdram)

		lis	r7, HIADJ( upmaTableSdramEnd)
		addi	r7, r7, LO(upmaTableSdramEnd)

		/* init UPMA for memory access */

		sub	r5, r7, r6		/* compute table size */
		srawi	r5, r5, 2		/* in integer size */

		/* convert UpmTable to ROM based addressing */

		lis	r7, HIADJ(romInit)	
		addi	r7, r7, LO(romInit)

		lis	r8, HIADJ(ROM_TEXT_ADRS)
		addi	r8, r8, LO(ROM_TEXT_ADRS)

		sub	r6, r6, r7		/* subtract romInit base address */
		add	r6, r6, r8 		/* add in ROM_TEXT_ADRS address */

					/* Command: OP=Write, UPMA, MAD=0 */
		lis	r9, HIADJ (MCR_OP_WRITE | MCR_UM_MB)
		addi	r9, r9, LO(MCR_OP_WRITE | MCR_UM_MB)

UpmaWriteLoop:	
		/* write the UPM table in the UPM */

		lwz	r10, 0(r6)		/* get data from table */
		stw	r10, MDR(0)(r4)		/* store the data to MD register */

		stw	r9, MCR(0)(r4)		/* issue command to MCR register */

		addi	r6, r6, 4		/* next entry in the table */
		addi	r9, r9, 1		/* next MAD address */	

    addi    r5,r5,-1
    cmpwi   r5,0
    bne     UpmaWriteLoop

		/***************************************************************************
		*
	 	*Initialize the sdram
	 	*
	 	****************************************************************************/	

		/* 
		* Issue precharge command (PRCG) and wait the precharge time (t-rp).
		* Run precharge pattern from UPMA location 5.
		*/

    lis     r5, HIADJ( 0x00000105 |MCR_OP_RUN | MCR_UM_MB)
    addi    r5, r5, LO( 0x00000105 |MCR_OP_RUN | MCR_UM_MB)
    stw     r5, MCR(0)(r4)
 
    /* run refresh pattern 8 times */

    lis     r5, HIADJ( 0x00000830 |MCR_OP_RUN | MCR_UM_MB)
    addi    r5, r5, LO( 0x00000830 |MCR_OP_RUN | MCR_UM_MB)
    stw     r5, MCR(0)(r4)        

		/* 
	 	* Configure the 32 bit address to be output on the address bus 
	 	* if AMX = 0xb11.
    * See section 16.6.4.1 "Arm Words".  The following values must 
	 	* be placed on the defined SDRAM address pins:
		*   A[9]   = 0          burst write mode
		*   A[6:4] = 010        cas latency of two
		*   A[3]   = 0          sequential mode
		*   A[2:0] = 010        burst length 4
		*
		* The address must be shifted left by 2 bits for 32 bit wide SDRAM...
		*   (0b0100010 << 2) = 0x88
    */

    lis     r5, HIADJ(LOCAL_MEM_LOCAL_ADRS | 0x88)
    addi    r5, r5, LO(LOCAL_MEM_LOCAL_ADRS | 0x88)
    stw     r5, MAR(0)(r4)
	
    /* 
    * issue a mode register set (MSR) to initialize the SDRAM mode 
    * register.  This programs the burst length, CAS latency and 
    * write mode. Run MRS pattern from UPMA location 6.
    */

    lis     r5, HIADJ(0x00000106 |MCR_OP_RUN | MCR_UM_MB)
    addi    r5, r5, LO(0x00000106 |MCR_OP_RUN | MCR_UM_MB)
    stw     r5, MCR(0)(r4)	

    /*
    * Map the bank 1 to the the sdram on the board 
    */

    lis	r5, HIADJ( 0xff000a00 )
    addi	r5, r5, LO( 0xff000a00 )
    stw	r5, OR1(0)(r4)	
	
    lis	r5, HIADJ( (LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMA | BR_V)
    addi	r5, r5, LO((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMA | BR_V)
    stw	r5, BR1(0)(r4)
        
    /* enable SDRAM refresh cycles */

    lis     r5, HIADJ (0xD0802111)
    addi    r5, r5,LO (0xD0802111)
    stw     r5, MAMR(0)(r4)

#if 1
    /* enable I cache */
    lis	r4, HIADJ ( CACHE_CMD_ENABLE)		/* load disable cmd */
    addi	r4, r4, LO (CACHE_CMD_ENABLE)
    mtspr	IC_CST, r4				/* enable I cache */
#endif        
    /* initialize the stack pointer */
	
    lis	sp, HIADJ(STACK_ADRS)
    addi	sp, sp, LO(STACK_ADRS)

	 /* go to C entry point */

    addi	sp, sp, -FRAMEBASESZ		/* get frame stack */

	 /* 
	  * calculate C entry point: routine - entry point + ROM base 
	  * routine	= romStart
	  * entry point	= romInit	= R7
	  * ROM base	= ROM_TEXT_ADRS = R8
	  * C entry point: romStart - R7 + R8 
	  */

    lis	r6, HIADJ(romStart)	
    addi	r6, r6, LO(romStart)	/* load R6 with C entry point */

	  sub	r6, r6, r7		/* routine - entry point */
	  add	r6, r6, r8 		/* + ROM base */

	  mtlr	r6			/* move C entry point to LR */	

	  blr				/* jump to the C entry point */

		/* This 50 MHz SDRAM table is for...
 	  *   860EN Rev B.1 9829 and newer silicon
 	  *   860T  Rev B.3 9832 and newer silicon
 	  * This table will NOT work with older 860EN or 860T parts.
		*/

#ifdef ADS860_RAMTABLE

upmaTableSdram:
 
/* single read   (offset 0x00 in upm ram) & init (offset 0x05 in upm ram)*/
       .long   0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00
       .long   0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35
/* burst read    (offset 0x08 in upm ram) */
       .long   0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00
       .long   0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* single write  (offset 0x18 in upm ram) */
       .long   0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* burst write   (offset 0x20 in upm ram) */
       .long   0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00
       .long   0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* refresh       (offset 0x30 in upm ram) */
       .long   0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* exception     (offset 0x3C in upm ram) */
       .long   0x7ffffc07, 0xfffffc04, 0xfffffc04, 0xfffffc04
 
upmaTableSdramEnd:
#endif

#ifdef MICRON_RAMTABLE
upmaTableSdram:
/* single read   (offset 0x00 in upm ram) & init (offset 0x05 in upm ram)*/
       .long   0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00
       .long   0x1ffffc05, 0x1ff77c35, 0xefeabc34, 0x1fb57c35
/* burst read    (offset 0x08 in upm ram) */
       .long   0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00
       .long   0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* single write  (offset 0x18 in upm ram) */
       .long   0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04
       .long   0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04
/* burst write   (offset 0x20 in upm ram) */
       .long   0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00
       .long   0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04
       .long   0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* refresh       (offset 0x30 in upm ram) */
       .long   0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04
       .long   0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* exception     (offset 0x3C in upm ram) */
       .long   0x7ffffc07, 0xfffffc04, 0xfffffc04, 0xfffffc04
upmaTableSdramEnd:
#endif /* MICRON_RAMTABLE  */