sgrwm7040.h

（1）本人基于MPC860的vxworks bsp的程序 （2）实现了FEC 100M和 SCC 10M的网口功能 （3）实现了nor flash的TFFS文件系统 （4）实现了系统的自检 （

/* sgrwm7040.h - Powercn SGR-WM7040 board header */

/*
modification history
--------------------
01a, 30apr05, GR1660 written.
*/

/*
This file contains I/O addresses, memory control and related constants for the
HHPPC860-3COM-2ETH-R1board board. 
*/

#ifndef	INCsgrwm7040h
#define	INCsgrwm7040h

#include "drv/mem/memDev.h"
#include "drv/intrCtl/ppc860Intr.h"


#define BUS	0				/* bus-less board */
#define CPU	PPC860				/* CPU type */

#define N_SIO_CHANNELS	 	2		/* No. serial I/O channels */

#define FREQ_25_MHZ		25000000	/* 25 Mhz */
#define FREQ_30_MHZ		30000000	/* 30 Mhz */
#define FREQ_35_MHZ		35000000	/* 35 Mhz */
#define FREQ_50_MHZ		50000000	/* 50 Mhz */


#define	PC_BASE_ADRS_0		0x02000000	/* PCMCIA base address */
#define	PC_SIZE_0		0x00100000	/* PCMCIA mapping size */
#define	PC_BASE_ADRS_1		0x04000000	/* PCMCIA base address */
#define	PC_SIZE_1		0x02000000	/* PCMCIA mapping size */

/* 
 * SPLL Multiplication Factor: use to set the MF bits of the PLPRCR register.
 * PLPRCR is set by sysHwInit() in sysLib.c. 
 * SPLL_FREQ_REQUESTED and CRISTAL_FREQ are defined in config.h
 */

#define SPLL_MUL_FACTOR	((SPLL_FREQ_REQUESTED / CRISTAL_FREQ) - 1)

/* 
 * SPLL Multiplication Factor to get a 20 MHZ running frequency
 */

#define SPLL_MUL_FACTOR_20MHZ	((FREQ_20_MHZ / CRISTAL_FREQ) - 1)

/*
 * SPLL Frequency - gives the SPLL real frequency divide by 2
 */

#define SPLL_FREQ	((SPLL_MUL_FACTOR + 1) * CRISTAL_FREQ)

/*
 * Baud Rate Generator Clock - gives the Baud Rate Generator Clock (BRGCLK)
 * Frequency. 
 */

#define BRGCLK_FREQ	(SPLL_FREQ / ( 1 << (2 * BRGCLK_DIV_FACTOR)))

/* 
 * Refresh value - defines the number of BRGCLK period between two 
 * DRAM refresh cycle.
 */

#define REFRESH_VALUE	(BRGCLK_FREQ / DRAM_REFRESH_FREQ)

/* 
 * Periodic Timer A period - value used to set the PTA bits of
 * the Machine A Mode Register (MAMR). This register is used to
 * controle the User_Programmable Machine A (UPM). The UPM is part of
 * the memory controller.
 */

#define PTA_VALUE	(( REFRESH_VALUE / 64) != 0 ? (REFRESH_VALUE / 64) : \
			 ((REFRESH_VALUE / 32) != 0 ? (REFRESH_VALUE / 32) : \
			 ((REFRESH_VALUE / 16) != 0 ? (REFRESH_VALUE / 16) : \
			 ((REFRESH_VALUE /  8) != 0 ? (REFRESH_VALUE /  8) : \
			 ((REFRESH_VALUE /  4) != 0 ? (REFRESH_VALUE /  4) : \
			  (REFRESH_VALUE /  2))))))

/* 
 * Periodic Timer Prescaler Division Factor - gives the division factor
 * of the Periodic Timer Prescaler (PTP). The PTP is part of the 
 * memory controller. It divide the BRGCLK (Baud Rate Generator Clock) by
 * either 2, 4, 8, 16, 32 or 64 and send this divided clock to the
 * Periodic Timer. 
 * This macro is used to set the DRAM refresh cycle period.
 */

#define PTP_DIV_FACTOR	(REFRESH_VALUE / PTA_VALUE)

/*
 * PTP Value - translate the Periodic Timer Prescaler Division Factor 
 * to the value to place in the PTP register.
 */

#define PTP_VALUE	( PTP_DIV_FACTOR ==  2 ? MPTPR_PTP_DIV2 : \
			 (PTP_DIV_FACTOR ==  4 ? MPTPR_PTP_DIV4 : \
			 (PTP_DIV_FACTOR ==  8 ? MPTPR_PTP_DIV8 : \
			 (PTP_DIV_FACTOR == 16 ? MPTPR_PTP_DIV16 : \
			 (PTP_DIV_FACTOR == 32 ? MPTPR_PTP_DIV32 : \
			  MPTPR_PTP_DIV64)))))

/* */

#define TMBCLK_FREQ	CRISTAL_FREQ

/* define the decrementer input clock frequency */

#define DEC_CLOCK_FREQ	TMBCLK_FREQ


/* define system clock rate */

#define	SYS_CPU_FREQ	SPLL_FREQ

/* Internal Memory Map base Address */
#define INTERNAL_MEM_MAP_ADDR		0x40000000	

#define INTERNAL_MEM_MAP_SIZE		0x00010000	/* 64 K bytes */

/* size of the on-board SDRAM */

#define SDRAM_SIZE			0x00400000	/* 4 Meg */
#define SDRAM_REFRESH_FREQ		64000		/* 64 Khz */

/* Port A pin map */

#define	PA00	0x08000
#define	PA01	0x04000
#define	PA02	0x02000
#define	PA03	0x01000
#define	PA04	0x08800
#define	PA05	0x00400
#define	PA06	0x00200
#define	PA07	0x00100
#define	PA08	0x00080
#define	PA09	0x00040
#define	PA10	0x00020
#define	PA11	0x00010
#define	PA12	0x00008
#define	PA13	0x00004
#define	PA14	0x00002
#define	PA15	0x00001

/* Port B pin map */

#define	PB14	0x20000
#define	PB15	0x10000
#define	PB16	0x08000
#define	PB17	0x04000
#define	PB18	0x02000
#define	PB19	0x01000
#define	PB20	0x00800
#define	PB21	0x00400
#define	PB22	0x00200
#define	PB23	0x00100
#define	PB24	0x00080
#define	PB25	0x00040
#define	PB26	0x00020
#define	PB27	0x00010
#define	PB28	0x00008
#define	PB29	0x00004
#define	PB30	0x00002
#define	PB31	0x00001

/* Port C pin map */

#define	PC04	0x00800
#define	PC05	0x00400
#define	PC06	0x00200
#define	PC07	0x00100
#define	PC08	0x00080
#define	PC09	0x00040
#define	PC10	0x00020
#define	PC11	0x00010
#define	PC12	0x00008
#define	PC13	0x00004
#define	PC14	0x00002
#define	PC15	0x00001

/* CPU type in the PVR */

#define CPU_TYPE_860			0x0050		/* value for PPC860 */
#define	CPU_REV_A1_MASK_NUM		0x0010		/* revision mask num */

/* Ethernet parameters */

#ifdef  INCLUDE_CPM				/* CPM ethernet driver */

#define INCLUDE_IF_USR
#define IF_USR_NAME     "cpm"                   /* device name */
#define IF_USR_ATTACH   sysCpmAttach            /* driver attach routine */
						/* address of SCC param RAM */
#define IF_USR_ARG1     (char *) INTERNAL_MEM_MAP_ADDR + 0x3c00 
#define IF_USR_823ARG1  (char *) INTERNAL_MEM_MAP_ADDR + 0x3d00 
						/* address of SCC regs */
#define IF_USR_ARG2     (int)INTERNAL_MEM_MAP_ADDR + 0x0a00    
#define IF_USR_823ARG2  (int)INTERNAL_MEM_MAP_ADDR + 0x0a20

#define IF_USR_ARG3     (int) IV_SCC1           /* int number for SCC1 */
#define IF_USR_823ARG3  (int) IV_SCC2           /* int number for SCC2 */
						/* address of transmit BDs */
#define IF_USR_ARG4     (int) INTERNAL_MEM_MAP_ADDR + 0x2000
						/* address of receive BDs */
#define IF_USR_ARG5     (int) INTERNAL_MEM_MAP_ADDR + 0x2100
#define IF_USR_ARG6     (int) 0x20              /* number of transmit BDs */
#define IF_USR_ARG7     (int) 0x20              /* number of receive BDs */
#define IF_USR_ARG8     (int) NONE              /* allocate mem for buffers */

#endif  /* INCLUDE_CPM */

#define WM7040_ZL50114_BASE 0x60000000
#define WM7040_ZL50114_SIZE  0x01000000

#define WM7040_DS21455_BASE 0x80000000


#endif /* INCsgrwm7040h */