📄 at91rm9200.h
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AT91_REG PIOD_IFDR; // Input Filter Disable Register
AT91_REG PIOD_IFSR; // Input Filter Status Register
AT91_REG Reserved29[1]; //
AT91_REG PIOD_SODR; // Set Output Data Register
AT91_REG PIOD_CODR; // Clear Output Data Register
AT91_REG PIOD_ODSR; // Output Data Status Register
AT91_REG PIOD_PDSR; // Pin Data Status Register
AT91_REG PIOD_IER; // Interrupt Enable Register
AT91_REG PIOD_IDR; // Interrupt Disable Register
AT91_REG PIOD_IMR; // Interrupt Mask Register
AT91_REG PIOD_ISR; // Interrupt Status Register
AT91_REG PIOD_MDER; // Multi-driver Enable Register
AT91_REG PIOD_MDDR; // Multi-driver Disable Register
AT91_REG PIOD_MDSR; // Multi-driver Status Register
AT91_REG Reserved30[1]; //
AT91_REG PIOD_PPUDR; // Pull-up Disable Register
AT91_REG PIOD_PPUER; // Pull-up Enable Register
AT91_REG PIOD_PPUSR; // Pad Pull-up Status Register
AT91_REG Reserved31[1]; //
AT91_REG PIOD_ASR; // Select A Register
AT91_REG PIOD_BSR; // Select B Register
AT91_REG PIOD_ABSR; // AB Select Status Register
AT91_REG Reserved32[9]; //
AT91_REG PIOD_OWER; // Output Write Enable Register
AT91_REG PIOD_OWDR; // Output Write Disable Register
AT91_REG PIOD_OWSR; // Output Write Status Register
AT91_REG Reserved33[85]; //
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved34[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved35[1]; //
AT91_REG CKGR_MOR; // Main Oscillator Register
AT91_REG CKGR_MCFR; // Main Clock Frequency Register
AT91_REG CKGR_PLLAR; // PLL A Register
AT91_REG CKGR_PLLBR; // PLL B Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved36[3]; //
AT91_REG PMC_PCKR[8]; // Programmable Clock Register
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved37[36]; //
AT91_REG ST_CR; // Control Register
AT91_REG ST_PIMR; // Period Interval Mode Register
AT91_REG ST_WDMR; // Watchdog Mode Register
AT91_REG ST_RTMR; // Real-time Mode Register
AT91_REG ST_SR; // Status Register
AT91_REG ST_IER; // Interrupt Enable Register
AT91_REG ST_IDR; // Interrupt Disable Register
AT91_REG ST_IMR; // Interrupt Mask Register
AT91_REG ST_RTAR; // Real-time Alarm Register
AT91_REG ST_CRTR; // Current Real-time Register
AT91_REG Reserved38[54]; //
AT91_REG RTC_CR; // Control Register
AT91_REG RTC_MR; // Mode Register
AT91_REG RTC_TIMR; // Time Register
AT91_REG RTC_CALR; // Calendar Register
AT91_REG RTC_TIMALR; // Time Alarm Register
AT91_REG RTC_CALALR; // Calendar Alarm Register
AT91_REG RTC_SR; // Status Register
AT91_REG RTC_SCCR; // Status Clear Command Register
AT91_REG RTC_IER; // Interrupt Enable Register
AT91_REG RTC_IDR; // Interrupt Disable Register
AT91_REG RTC_IMR; // Interrupt Mask Register
AT91_REG RTC_VER; // Valid Entry Register
AT91_REG Reserved39[52]; //
AT91_REG MC_RCR; // MC Remap Control Register
AT91_REG MC_ASR; // MC Abort Status Register
AT91_REG MC_AASR; // MC Abort Address Status Register
AT91_REG Reserved40[1]; //
AT91_REG MC_PUIA[16]; // MC Protection Unit Area
AT91_REG MC_PUP; // MC Protection Unit Peripherals
AT91_REG MC_PUER; // MC Protection Unit Enable Register
AT91_REG Reserved41[2]; //
AT91_REG EBI_CSA; // Chip Select Assignment Register
AT91_REG EBI_CFGR; // Configuration Register
AT91_REG Reserved42[2]; //
AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register
AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register
AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG EBI_SDRC_CR; // SDRAM Controller Configuration Register
AT91_REG EBI_SDRC_SRR; // SDRAM Controller Self Refresh Register
AT91_REG EBI_SDRC_LPR; // SDRAM Controller Low Power Register
AT91_REG EBI_SDRC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG Reserved43[3]; //
AT91_REG EBI_BFC_MR; // BFC Mode Register
} AT91S_SYS, *AT91PS_SYS;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Memory Controller Interface
// *****************************************************************************
typedef struct _AT91S_MC {
AT91_REG MC_RCR; // MC Remap Control Register
AT91_REG MC_ASR; // MC Abort Status Register
AT91_REG MC_AASR; // MC Abort Address Status Register
AT91_REG Reserved0[1]; //
AT91_REG MC_PUIA[16]; // MC Protection Unit Area
AT91_REG MC_PUP; // MC Protection Unit Peripherals
AT91_REG MC_PUER; // MC Protection Unit Enable Register
} AT91S_MC, *AT91PS_MC;
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_MPU ((unsigned int) 0x1 << 2) // (MC) Memory protection Unit Abort Status
#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
#define AT91C_MC_PROT ((unsigned int) 0x3 << 0) // (MC) Protection
#define AT91C_MC_PROT_PNAUNA (unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access
#define AT91C_MC_PROT_PRWUNA ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access
#define AT91C_MC_PROT_PRWURO ((unsigned int) 0x2) // (MC) Privilege: Read/Write, User: Read Only
#define AT91C_MC_PROT_PRWURW ((unsigned int) 0x3) // (MC) Privilege: Read/Write, User: Read/Write
#define AT91C_MC_SIZE ((unsigned int) 0xF << 4) // (MC) Internal Area Size
#define AT91C_MC_SIZE_1KB ((unsigned int) 0x0 << 4) // (MC) Area size 1KByte
#define AT91C_MC_SIZE_2KB ((unsigned int) 0x1 << 4) // (MC) Area size 2KByte
#define AT91C_MC_SIZE_4KB ((unsigned int) 0x2 << 4) // (MC) Area size 4KByte
#define AT91C_MC_SIZE_8KB ((unsigned int) 0x3 << 4) // (MC) Area size 8KByte
#define AT91C_MC_SIZE_16KB ((unsigned int) 0x4 << 4) // (MC) Area size 16KByte
#define AT91C_MC_SIZE_32KB ((unsigned int) 0x5 << 4) // (MC) Area size 32KByte
#define AT91C_MC_SIZE_64KB ((unsigned int) 0x6 << 4) // (MC) Area size 64KByte
#define AT91C_MC_SIZE_128KB ((unsigned int) 0x7 << 4) // (MC) Area size 128KByte
#define AT91C_MC_SIZE_256KB ((unsigned int) 0x8 << 4) // (MC) Area size 256KByte
#define AT91C_MC_SIZE_512KB ((unsigned int) 0x9 << 4) // (MC) Area size 512KByte
#define AT91C_MC_SIZE_1MB ((unsigned int) 0xA << 4) // (MC) Area size 1MByte
#define AT91C_MC_SIZE_2MB ((unsigned int) 0xB << 4) // (MC) Area size 2MByte
#define AT91C_MC_SIZE_4MB ((unsigned int) 0xC << 4) // (MC) Area size 4MByte
#define AT91C_MC_SIZE_8MB ((unsigned int) 0xD << 4) // (MC) Area size 8MByte
#define AT91C_MC_SIZE_16MB ((unsigned int) 0xE << 4) // (MC) Area size 16MByte
#define AT91C_MC_SIZE_64MB ((unsigned int) 0xF << 4) // (MC) Area size 64MByte
#define AT91C_MC_BA ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address
// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
#define AT91C_MC_PUEB ((unsigned int) 0x1 << 0) // (MC) Protection Unit enable Bit
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface
// *****************************************************************************
typedef struct _AT91S_RTC {
AT91_REG RTC_CR; // Control Register
AT91_REG RTC_MR; // Mode Register
AT91_REG RTC_TIMR; // Time Register
AT91_REG RTC_CALR; // Calendar Register
AT91_REG RTC_TIMALR; // Time Alarm Register
AT91_REG RTC_CALALR; // Calendar Alarm Register
AT91_REG RTC_SR; // Status Register
AT91_REG RTC_SCCR; // Status Clear Command Register
AT91_REG RTC_IER; // Interrupt Enable Register
AT91_REG RTC_IDR; // Interrupt Disable Register
AT91_REG RTC_IMR; // Interrupt Mask Register
AT91_REG RTC_VER; // Valid Entry Register
} AT91S_RTC, *AT91PS_RTC;
// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register --------
#define AT91C_RTC_UPDTIM ((unsigned int) 0x1 << 0) // (RTC) Update Request Time Register
#define AT91C_RTC_UPDCAL ((unsigned int) 0x1 << 1) // (RTC) Update Request Calendar Register
#define AT91C_RTC_TIMEVSEL ((unsigned int) 0x3 << 8) // (RTC) Time Event Selection
#define AT91C_RTC_TIMEVSEL_MINUTE ((unsigned int) 0x0 << 8) // (RTC) Minute change.
#define AT91C_RTC_TIMEVSEL_HOUR ((unsigned int) 0x1 << 8) // (RTC) Hour change.
#define AT91C_RTC_TIMEVSEL_DAY24 ((unsigned int) 0x2 << 8) // (RTC) Every day at midnight.
#define AT91C_RTC_TIMEVSEL_DAY12 ((unsigned int) 0x3 << 8) // (RTC) Every day at noon.
#define AT91C_RTC_CALEVSEL (unsigned int) 0x3 << 16) // (RTC) Calendar Event Selection
#define AT91C_RTC_CALEVSEL_WEEK ((unsigned int) 0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).
#define AT91C_RTC_CALEVSEL_MONTH ((unsigned int) 0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).
#define AT91C_RTC_CALEVSEL_YEAR ((unsigned int) 0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).
// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register --------
#define AT91C_RTC_HRMOD ((unsigned int) 0x1 << 0) // (RTC) 12-24 hour Mode
// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register --------
#define AT91C_RTC_SEC ((unsigned int) 0x7F << 0) // (RTC) Current Second
#define AT91C_RTC_MIN ((unsigned int) 0x7F << 8) // (RTC) Current Minute
#define AT91C_RTC_HOUR ((unsigned int) 0x1F << 16) // (RTC) Current Hour
#define AT91C_RTC_AMPM ((unsigned int) 0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator
// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register --------
#define AT91C_RTC_CENT ((unsigned int) 0x3F << 0) // (RTC) Current Century
#define AT91C_RTC_YEAR ((unsigned int) 0xFF << 8) // (RTC) Current Year
#define AT91C_RTC_MONTH ((unsigned int) 0x1F << 16) // (RTC) Current Month
#define AT91C_RTC_DAY ((unsigned int) 0x7 << 21) // (RTC) Current Day
#define AT91C_RTC_DATE ((unsigned int) 0x3F << 24) // (RTC) Current Date
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