at91sio.c

(1)基于部分u-boot代码自己调试的vxworks BSP (2)实现了nand/nor flash的tffs文件系统 (3)实现了对spi dataflash的访问 (4)实现了对启动参数

           AT91_UCON_TMODE_CPU |                         /* CPU Request */
#ifdef  UARTCLK_EXTERNAL
           AT91_UCON_SCSEL_UCLK;                         /* External */
#else   /* UARTCLK_EXTERNAL */
           AT91_UCON_SCSEL_PCLK2;                        /* Internal (PCLK2 = PCLK / 2) */
#endif  /* UARTCLK_EXTERNAL */

    /* Set character size. */
    switch (options & CSIZE)
    {
    case CS5:
        ucon |= AT91_UCON_WL_5;                          /* 5 Bits */
        break;

    case CS6:
        ucon |= AT91_UCON_WL_6;                          /* 6 Bits */
        break;

    case CS7:
        ucon |= AT91_UCON_WL_7;                          /* 7 Bits */
        break;

    case CS8:
        ucon |= AT91_UCON_WL_8;                          /* 8 Bits */
        break;
    }

    /* Set stop bits. */
    if (!(options & STOPB))                                 /* send two stop bits (else one) */
    {
        ucon |= AT91_UCON_STB_1;                         /* One Stop Bit per Frame */
    }
    else
    {
        ucon |= AT91_UCON_STB_2;                         /* Two Stop Bit per Frame */
    }

    /* Set parity. */
    if (!(options & PARENB))                                /* parity detection enabled (else disabled) */
    {
        ucon |= AT91_UCON_PMD_NO;                        /* No Parity */
    }
    else
    {
        if (options & PARODD)                               /* odd parity  (else even) */
        {
            ucon |= AT91_UCON_PMD_ODD;                   /* Odd Parity */
        }
        else
        {
            ucon |= AT91_UCON_PMD_EVEN;                  /* Even Parity */
        }
    }

    if (pChan->ch != 0)                                     /* high-speed UART. */
    {
        ucon |= AT91_HUCON_RFTL_28 |                     /* Receive FIFO Trigger Level */
                AT91_HUCON_TFTL_16 |                     /* Transmit FIFO Trigger Level */
                AT91_HUCON_RFEN |                        /* Receive FIFO Enable */
                AT91_HUCON_TFEN;                         /* Transmit FIFO Enable */

        if (!(options & CLOCAL))                            /* ignore modem status lines */
        {
            ucon |= AT91_HUCON_HFEN |                    /* Hardware Flow Control Enable */
                    AT91_HUCON_RTSRTR_RTS |              /* RTS/RTR Selection */
                    AT91_HUCON_DTR;                      /* Data Terminal Ready to Pin */
        }
    }

    /* Write UART Control Register. */
    *AT91_UCON(pChan->ch) = ucon;
#endif

/*  unsigned long flags;*/
  unsigned int mode, imr;
  AT91PS_USART port =(AT91PS_USART) (pChan->base);
  
  /* Get current mode register */
  mode = port->US_MR & ~(AT91C_US_CHRL | AT91C_US_NBSTOP | AT91C_US_PAR);

	/* byte size */
	switch (options & CSIZE) {
	case CS5:
		mode |= AT91C_US_CHRL_5_BITS;
		break;
	case CS6:
		mode |= AT91C_US_CHRL_6_BITS;
		break;
	case CS7:
		mode |= AT91C_US_CHRL_7_BITS;
		break;
	default:
		mode |= AT91C_US_CHRL_8_BITS;
		break;
	}

	/* stop bits */
	if (options & STOPB)
		mode |= AT91C_US_NBSTOP_2_BIT;

	/* parity */
	if (options & PARENB) {
		if (options & PARENB) {			/* Mark or Space parity */
			if (options & PARODD)
				mode |= AT91C_US_PAR_MARK;
			else
				mode |= AT91C_US_PAR_SPACE;
		}
		else if (options & PARODD)
			mode |= AT91C_US_PAR_ODD;
		else
			mode |= AT91C_US_PAR_EVEN;
	}
	else
		mode |= AT91C_US_PAR_NONE;




	/* TODO: Ignore all characters if CREAD is set.*/

	/* first, disable interrupts and drain transmitter */
	/*local_irq_save(flags);*/
	imr = UART_GET_IMR(port);	/* get interrupt mask */
	UART_PUT_IDR(port, -1);		/* disable all interrupts */
	/*local_irq_restore(flags);*/
	/*while (!(UART_GET_CSR(port) & AT91C_US_TXEMPTY)) { barrier(); }*/

	/* disable receiver and transmitter */
	UART_PUT_CR(port, AT91C_US_TXDIS | AT91C_US_RXDIS);

	/* set the parity, stop bits and data size */
	UART_PUT_MR(port, mode);

	/* set the baud rate */
/*	UART_PUT_BRGR(port, quot);*/
	UART_PUT_CR(port, AT91C_US_TXEN | AT91C_US_RXEN);

	/* restore interrupts */
	UART_PUT_IER(port, imr);

	/* CTS flow-control and modem-status interrupts */
	/*if (UART_ENABLE_MS(port, cflag))*/
	/*	at91_pops.enable_ms(port);*/
    pChan->options = options;

    return OK;
}

/******************************************************************************
*
* at91SioModeSet - set the channel's SIO mode
*
* RETURNS: OK on success, ENOSYS on unsupported request, EIO on failed request.
*/

LOCAL int at91SioModeSet(
    AT91_SIO_CHAN *pChan,                                /* device to control */
    int sioMode                                             /* SIO mode */
    )
{
  
    AT91PS_USART uart =(AT91PS_USART) (pChan->base);
    
    if ((sioMode != SIO_MODE_POLL) && (sioMode != SIO_MODE_INT))
    {
        return EIO;
    }   
 
    if (sioMode == SIO_MODE_INT) /* interrupt mode */
    {
        uart->US_IDR = AT91C_US_RXRDY   	|
                   AT91C_US_TXRDY       |
                   AT91C_US_ENDRX       |
                   AT91C_US_ENDTX       |
                   AT91C_US_OVRE    	|
                   AT91C_US_FRAME       |
                   AT91C_US_PARE        |
                   AT91C_US_TXEMPTY     |
                   AT91C_US_TXBUFE  	|
                   AT91C_US_RXBUFF      |
                   AT91C_US_COMM_TX     |
                   AT91C_US_COMM_RX  	|
                   AT91C_US_TIMEOUT	; 
		#ifdef AT91C_DBGU_PDC_MODE
		uart->US_IER = AT91C_US_RXRDY;

        /* Create a sem4 for the pdc interrupt mode */
		if (semDbguPdcTx == NULL)
		{
            semDbguPdcTx = semBCreate (SEM_Q_FIFO, SEM_FULL);
			if (semDbguPdcTx == NULL)
			    return 	EIO;
		}

        /* malloc cache-safe memory for the dbgu pdc */
        dbgupdctxbuffer = cacheDmaMalloc(DBGU_PDC_TXBUFFER_LENGTH);
		if (dbgupdctxbuffer == NULL)
		    return 	EIO;	
		
		#else /* AT91C_DBGU_PDC_MODE */
        uart->US_IER = AT91C_US_RXRDY | AT91C_US_TXEMPTY;  
		#endif /* AT91C_DBGU_PDC_MODE */
    }
    else  /* polling mode */
    {
        uart->US_IDR = AT91C_US_RXRDY   	|
                   AT91C_US_TXRDY       |
                   AT91C_US_ENDRX       |
                   AT91C_US_ENDTX       |
                   AT91C_US_OVRE    	|
                   AT91C_US_FRAME       |
                   AT91C_US_PARE        |
                   AT91C_US_TXEMPTY     |
                   AT91C_US_TXBUFE  	|
                   AT91C_US_RXBUFF      |
                   AT91C_US_COMM_TX     |
                   AT91C_US_COMM_RX  	|
                   AT91C_US_TIMEOUT	;                        
    }

    pChan->sioMode = sioMode;

    return OK;
}

/******************************************************************************
*
* at91SioOpen - set the modem control lines 
*
* Set the modem control lines(RTS, DTR) TRUE if not already set.
*
* RETURNS: OK on success, ENOSYS on unsupported request, EIO on failed request.
*/

LOCAL int at91SioOpen(
    AT91_SIO_CHAN *pChan                                 /* device to control */
    )
{
    AT91PS_USART uart =(AT91PS_USART) (pChan->base);

    if (pChan->base == (void*) AT91C_BASE_DBGU )                                     /* console UART */
    {
        return ENOSYS;
    }

    if (!(pChan->options & HUPCL))                          /* hang up on last close */
    {
        return ENOSYS;
    }

    if (pChan->options & CLOCAL)                            /* ignore modem status lines */
    {
        return ENOSYS;
    }

    /* Asserts DTR. */
    uart->US_CR |=AT91C_US_DTREN;  			/* Data Terminal Ready to Pin */	


    return OK;
}

/******************************************************************************
*
* at91SioHup - hang up the modem control lines 
*
* Resets the RTS and DTR signals.
*
* RETURNS: OK on success, ENOSYS on unsupported request, EIO on failed request.
*/

LOCAL int at91SioHup(
    AT91_SIO_CHAN *pChan                                 /* device to control */
    )
{
    AT91PS_USART uart =(AT91PS_USART) (pChan->base);
    if (uart == (AT91PS_USART)AT91C_BASE_DBGU)                                     /* console UART */
    {
        return ENOSYS;
    }

    if (!(pChan->options & HUPCL))                          /* hang up on last close */
    {
        return ENOSYS;
    }

    if (pChan->options & CLOCAL)                            /* ignore modem status lines */
    {
        return ENOSYS;
    }

    /* Deasserts DTR. */
        uart->US_CR &=~AT91C_US_DTREN;  			/* Data Terminal Ready to Pin */	

    return OK;
}


#ifdef AT91C_DBGU_PDC_MODE

unsigned int AT91C_DbguPdc_DeInit(void)
{
    AT91PS_PDC pPDC = (AT91PS_PDC) &(((AT91PS_USART) AT91C_BASE_DBGU)->US_RPR);

    /** Disable the RX and TX PDC transfer requests*/
	AT91F_PDC_DisableRx(pPDC);
	AT91F_PDC_DisableTx(pPDC);

	/** Reset all Counter register Next buffer first*/
	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);

	UART_PUT_IDR(((AT91PS_USART)AT91C_BASE_DBGU), AT91C_US_ENDTX);
 
    semDelete(semDbguPdcTx);
	semDbguPdcTx = NULL;

	cacheDmaFree(dbgupdctxbuffer);
	dbgupdctxbuffer = NULL;
	
    return 0;
}

LOCAL unsigned int AT91C_DbguPdc_Init(void)
{
    AT91PS_PDC pPDC = (AT91PS_PDC) &(((AT91PS_USART) AT91C_BASE_DBGU)->US_RPR);

    /** Disable the RX and TX PDC transfer requests*/
	AT91F_PDC_DisableRx(pPDC);
	AT91F_PDC_DisableTx(pPDC);

	/** Reset all Counter register Next buffer first*/
	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);

	UART_PUT_IDR(((AT91PS_USART)AT91C_BASE_DBGU), AT91C_US_ENDTX);
    /* Enable the TX PDC transfer requests */
	AT91F_PDC_EnableTx(pPDC);

	
    return 0;
}

LOCAL unsigned int AT91C_DbguPdc_Send_Frame_Start(char *pBuffer, unsigned int bytes_to_send )
{
    AT91PS_PDC pPDC = (AT91PS_PDC) &(((AT91PS_USART) AT91C_BASE_DBGU)->US_RPR);
    AT91F_PDC_SetTx(pPDC, pBuffer, bytes_to_send);		
	UART_PUT_IER(((AT91PS_USART)AT91C_BASE_DBGU), AT91C_US_ENDTX);

	return 0;
}


LOCAL unsigned int AT91C_DbguPdc_Send_Frame_Stop(void)
{
    UART_PUT_IDR(((AT91PS_USART)AT91C_BASE_DBGU), AT91C_US_ENDTX);
	return 0;
}

#endif /* AT91C_DBGU_PDC_MODE */