iodef.h

sanyo1787 and TEF6606 source code

// IO FUNCTION DEFINATION FOR LCD CONTROLLER 
// Pei Feng 2007/3/9
#include "mb95100.h"

#define   	ROTATOR_OK     	PDR0_P00
#define     	ROTATOR_INT      PDR0_P01
#define     	ROTATOR_READ   PDR0_P02		
#define     	CD_8V_ON		PDR0_P03
//#define  	CLIP_DET		PDR0_P04
#define     	CD_SUBSY 		PDR0_P04
#define		LVI_IN			PDR0_P05
#define 		ACC_IN			PDR0_P06  //Hole1-56
#define		PTA_IN			PDR0_P07

#define		CD_OPEN		PDR1_P10
#define     	CD_LOAD		PDR1_P11
#define		CD_LIM_SW		PDR1_P12
#define		CD_OK			PDR1_P13
#define		BEEP 			PDR1_P14

#define		CD_REV			PDR2_P20
#define		CD_FWD			PDR2_P21
#define		CD_RESET		PDR2_P22
#define		MEM_DQM		PDR2_P23
#define		AVC_IN			PDR2_P24


#define		SDA0 			PDR5_P50
#define		SCL0 			PDR5_P51
#define		PWR_ON			PDR5_P52  //Hole2-65
#define		CD_BUSY		PDR5_P53

#define		CD_RW			PDR3_P30
#define		SWC_IN			PDR3_P31    
#define		KEY_IN5			PDR3_P32
#define		KEY_IN4			PDR3_P33 
#define		KEY_IN3			PDR3_P34
#define 		KEY_IN2			PDR3_P35
#define		KEY_IN1			PDR3_P36
#define		S_METER		PDR3_P37

#define		PLL_PRD			PDR4_P40
#define		PLL_CLK			PDR4_P41
#define		PLL_DA			PDR4_P42
#define		SD_ST			PDR4_P43

#define		SCLK			PDR7_P70     //Hole2-69
#define     	SDA				PDR7_P71     //Hole2-73
#define     	SDA_OUT_INPUT   DDR7_D71	   //0:SDA input enable


#define		CD_DATA		PDR6_P67
#define		CD_MCK			PDR6_P65
//#define	CD_SUBSY            PDR6_P64  // ZHANG JIN CHANGED
/*

#define		SEG35			PDR6_P63
#define		SEG34			PDR6_P62
#define		SEG33			PDR6_P61
#define		SEG32			PDR6_P60

#define		SEG31			PDRE_PE7
#define		SEG30			PDRE_PE6
#define		SEG29			PDRE_PE5
#define		SEG28			PDRE_PE4
#define		SEG27			PDRE_PE3
#define		SEG26			PDRE_PE2
#define		SEG25			PDRE_PE1
#define		SEG24			PDRE_PE0

#define		SEG23			PDRD_PD7
#define		SEG22			PDRD_PD6
#define		SEG21			PDRD_PD5
#define		SEG20			PDRD_PD4
#define		SEG19			PDRD_PD3
#define		SEG18			PDRD_PD2
#define		SEG17			PDRD_PD1
#define		SEG16			PDRD_PD0

#define		SEG15			PDRC_PC7
#define		SEG14			PDRC_PC6
#define		SEG13			PDRC_PC5
#define		SEG12			PDRC_PC4
#define		SEG11			PDRC_PC3
#define		SEG10			PDRC_PC2
#define		SEG09			PDRC_PC1
#define		SEG08			PDRC_PC0

#define		SEG07			PDRB_PB7
#define		SEG06			PDRB_PB6
#define		SEG05			PDRB_PB5
#define		SEG04			PDRB_PB4
#define		SEG03			PDRB_PB3
#define		SEG02			PDRB_PB2
#define		SEG01			PDRB_PB1
#define		SEG00			PDRB_PB0

#define		COM3			PDRA_PA3
#define		COM2			PDRA_PA2
#define		COM1			PDRA_PA1
#define		COM0			PDRA_PA0  */

#define		AMP_MUTE			PDR9_P94   //Hole2-19
#define		AMP_STANDBY		PDR9_P95   //Hole2-16

#define     	DA_OUT_INPUT    DDR4_D42
#define     	PRD_OUT_INPUT   DDR4_D40
#define     	CLK_OUT_INPUT   DDR4_D41