📄 farmer.tan.rpt
字号:
; N/A ; None ; 32.000 ns ; farmer|CS.state_bit_1 ; out1[1] ; start ;
; N/A ; None ; 25.000 ns ; farmer|CS.state_bit_2 ; out2[1] ; start ;
; N/A ; None ; 25.000 ns ; farmer|CS.state_bit_4 ; out2[1] ; start ;
; N/A ; None ; 25.000 ns ; farmer|CS.state_bit_3 ; out2[1] ; start ;
; N/A ; None ; 25.000 ns ; farmer|CS.state_bit_1 ; out2[1] ; start ;
; N/A ; None ; 25.000 ns ; farmer|CS.state_bit_0 ; out2[3] ; start ;
; N/A ; None ; 25.000 ns ; farmer|CS.state_bit_4 ; out2[3] ; start ;
; N/A ; None ; 25.000 ns ; farmer|CS.state_bit_1 ; out2[3] ; start ;
; N/A ; None ; 25.000 ns ; farmer|CS.state_bit_0 ; out1[3] ; start ;
; N/A ; None ; 25.000 ns ; farmer|CS.state_bit_4 ; out1[3] ; start ;
; N/A ; None ; 25.000 ns ; farmer|CS.state_bit_1 ; out1[3] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_2 ; out2[2] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_0 ; out2[2] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_4 ; out2[2] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_3 ; out2[2] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_1 ; out2[2] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_0 ; out2[1] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_2 ; out2[0] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_0 ; out2[0] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_4 ; out2[0] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_3 ; out2[0] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_1 ; out2[0] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_2 ; out1[2] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_0 ; out1[2] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_4 ; out1[2] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_3 ; out1[2] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_1 ; out1[2] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_2 ; out1[0] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_0 ; out1[0] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_4 ; out1[0] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_3 ; out1[0] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_1 ; out1[0] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_2 ; out2[3] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_3 ; out2[3] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_2 ; out1[3] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_3 ; out1[3] ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_2 ; e0 ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_0 ; e0 ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_4 ; e0 ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_3 ; e0 ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_1 ; e0 ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_2 ; ok ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_4 ; ok ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_3 ; ok ; start ;
; N/A ; None ; 24.000 ns ; farmer|CS.state_bit_1 ; ok ; start ;
+-------+--------------+------------+-----------------------+---------+------------+
+------------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+-------+-----------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+-------+-----------------------+----------+
; N/A ; None ; 4.000 ns ; in[0] ; farmer|CS.state_bit_0 ; start ;
; N/A ; None ; 4.000 ns ; in[0] ; farmer|CS.state_bit_4 ; start ;
; N/A ; None ; 4.000 ns ; in[0] ; farmer|CS.state_bit_3 ; start ;
; N/A ; None ; 4.000 ns ; in[0] ; farmer|CS.state_bit_1 ; start ;
; N/A ; None ; 4.000 ns ; in[3] ; farmer|CS.state_bit_2 ; start ;
; N/A ; None ; 4.000 ns ; in[3] ; farmer|CS.state_bit_0 ; start ;
; N/A ; None ; 4.000 ns ; in[3] ; farmer|CS.state_bit_4 ; start ;
; N/A ; None ; 4.000 ns ; in[3] ; farmer|CS.state_bit_3 ; start ;
; N/A ; None ; 4.000 ns ; in[3] ; farmer|CS.state_bit_1 ; start ;
; N/A ; None ; 4.000 ns ; in[2] ; farmer|CS.state_bit_2 ; start ;
; N/A ; None ; 4.000 ns ; in[2] ; farmer|CS.state_bit_0 ; start ;
; N/A ; None ; 4.000 ns ; in[2] ; farmer|CS.state_bit_4 ; start ;
; N/A ; None ; 4.000 ns ; in[2] ; farmer|CS.state_bit_3 ; start ;
; N/A ; None ; 4.000 ns ; in[2] ; farmer|CS.state_bit_1 ; start ;
; N/A ; None ; 4.000 ns ; in[1] ; farmer|CS.state_bit_2 ; start ;
; N/A ; None ; 4.000 ns ; in[1] ; farmer|CS.state_bit_0 ; start ;
; N/A ; None ; 4.000 ns ; in[1] ; farmer|CS.state_bit_4 ; start ;
; N/A ; None ; 4.000 ns ; in[1] ; farmer|CS.state_bit_3 ; start ;
; N/A ; None ; 4.000 ns ; in[1] ; farmer|CS.state_bit_1 ; start ;
; N/A ; None ; 3.000 ns ; in[0] ; farmer|CS.state_bit_2 ; start ;
+---------------+-------------+-----------+-------+-----------------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Wed Nov 28 19:23:08 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off farmer -c farmer
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "start" is an undefined clock
Info: Clock "start" has Internal fmax of 66.67 MHz between source register "farmer|CS.state_bit_2" and destination register "farmer|CS.state_bit_2" (period= 15.0 ns)
Info: + Longest register to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer|CS.state_bit_2'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC30; Fanout = 1; COMB Node = 'farmer|CS.state_bit_2~478'
Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC31; Fanout = 1; COMB Node = 'farmer|CS.state_bit_2~483'
Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer|CS.state_bit_2'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "start" to destination register is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 5; CLK Node = 'start'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer|CS.state_bit_2'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: - Longest clock path from clock "start" to source register is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 5; CLK Node = 'start'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer|CS.state_bit_2'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "farmer|CS.state_bit_2" (data pin = "in[0]", clock pin = "start") is 6.000 ns
Info: + Longest pin to register delay is 12.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_12; Fanout = 38; PIN Node = 'in[0]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC30; Fanout = 1; COMB Node = 'farmer|CS.state_bit_2~478'
Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC31; Fanout = 1; COMB Node = 'farmer|CS.state_bit_2~483'
Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 12.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer|CS.state_bit_2'
Info: Total cell delay = 10.000 ns ( 83.33 % )
Info: Total interconnect delay = 2.000 ns ( 16.67 % )
Info: + Micro setup delay of destination is 4.000 ns
Info: - Shortest clock path from clock "start" to destination register is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 5; CLK Node = 'start'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer|CS.state_bit_2'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: tco from clock "start" to destination pin "out1[1]" through register "farmer|CS.state_bit_2" is 32.000 ns
Info: + Longest clock path from clock "start" to source register is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 5; CLK Node = 'start'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer|CS.state_bit_2'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 21.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer|CS.state_bit_2'
Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP35; Fanout = 1; COMB Node = 'WideOr2~39'
Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 17.000 ns; Loc. = LC46; Fanout = 1; COMB Node = 'WideOr2~40'
Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 21.000 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'out1[1]'
Info: Total cell delay = 19.000 ns ( 90.48 % )
Info: Total interconnect delay = 2.000 ns ( 9.52 % )
Info: th for register "farmer|CS.state_bit_0" (data pin = "in[0]", clock pin = "start") is 4.000 ns
Info: + Longest clock path from clock "start" to destination register is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 5; CLK Node = 'start'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC29; Fanout = 71; REG Node = 'farmer|CS.state_bit_0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: + Micro hold delay of destination is 4.000 ns
Info: - Shortest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_12; Fanout = 38; PIN Node = 'in[0]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC29; Fanout = 71; REG Node = 'farmer|CS.state_bit_0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Wed Nov 28 19:23:09 2007
Info: Elapsed time: 00:00:02
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