farmer.tan.qmsg

農夫過河

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "start " "Info: Assuming node \"start\" is an undefined clock" {  } { { "farmer.v" "" { Text "C:/altera/quartus60/win/farmer/farmer.v" 3 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "start" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "start register farmer\|CS.state_bit_2 register farmer\|CS.state_bit_2 66.67 MHz 15.0 ns Internal " "Info: Clock \"start\" has Internal fmax of 66.67 MHz between source register \"farmer\|CS.state_bit_2\" and destination register \"farmer\|CS.state_bit_2\" (period= 15.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest register register " "Info: + Longest register to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns farmer\|CS.state_bit_2 1 REG LC32 76 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer\|CS.state_bit_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { farmer|CS.state_bit_2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns farmer\|CS.state_bit_2~478 2 COMB LC30 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC30; Fanout = 1; COMB Node = 'farmer\|CS.state_bit_2~478'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { farmer|CS.state_bit_2 farmer|CS.state_bit_2~478 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns farmer\|CS.state_bit_2~483 3 COMB LC31 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC31; Fanout = 1; COMB Node = 'farmer\|CS.state_bit_2~483'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { farmer|CS.state_bit_2~478 farmer|CS.state_bit_2~483 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 10.000 ns farmer\|CS.state_bit_2 4 REG LC32 76 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer\|CS.state_bit_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { farmer|CS.state_bit_2~483 farmer|CS.state_bit_2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { farmer|CS.state_bit_2 farmer|CS.state_bit_2~478 farmer|CS.state_bit_2~483 farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { farmer|CS.state_bit_2 farmer|CS.state_bit_2~478 farmer|CS.state_bit_2~483 farmer|CS.state_bit_2 } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "start destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock \"start\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns start 1 CLK PIN_15 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 5; CLK Node = 'start'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "farmer.v" "" { Text "C:/altera/quartus60/win/farmer/farmer.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns farmer\|CS.state_bit_2 2 REG LC32 76 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer\|CS.state_bit_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { start start~out farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "start source 10.000 ns - Longest register " "Info: - Longest clock path from clock \"start\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns start 1 CLK PIN_15 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 5; CLK Node = 'start'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "farmer.v" "" { Text "C:/altera/quartus60/win/farmer/farmer.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns farmer\|CS.state_bit_2 2 REG LC32 76 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer\|CS.state_bit_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { start start~out farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { start start~out farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { start start~out farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { farmer|CS.state_bit_2 farmer|CS.state_bit_2~478 farmer|CS.state_bit_2~483 farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { farmer|CS.state_bit_2 farmer|CS.state_bit_2~478 farmer|CS.state_bit_2~483 farmer|CS.state_bit_2 } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 1.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { start start~out farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { start start~out farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "farmer\|CS.state_bit_2 in\[0\] start 6.000 ns register " "Info: tsu for register \"farmer\|CS.state_bit_2\" (data pin = \"in\[0\]\", clock pin = \"start\") is 6.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.000 ns + Longest pin register " "Info: + Longest pin to register delay is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns in\[0\] 1 PIN PIN_12 38 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_12; Fanout = 38; PIN Node = 'in\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { in[0] } "NODE_NAME" } } { "farmer.v" "" { Text "C:/altera/quartus60/win/farmer/farmer.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns farmer\|CS.state_bit_2~478 2 COMB LC30 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC30; Fanout = 1; COMB Node = 'farmer\|CS.state_bit_2~478'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { in[0] farmer|CS.state_bit_2~478 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 11.000 ns farmer\|CS.state_bit_2~483 3 COMB LC31 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC31; Fanout = 1; COMB Node = 'farmer\|CS.state_bit_2~483'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { farmer|CS.state_bit_2~478 farmer|CS.state_bit_2~483 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 12.000 ns farmer\|CS.state_bit_2 4 REG LC32 76 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 12.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer\|CS.state_bit_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { farmer|CS.state_bit_2~483 farmer|CS.state_bit_2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.000 ns" { in[0] farmer|CS.state_bit_2~478 farmer|CS.state_bit_2~483 farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.000 ns" { in[0] in[0]~out farmer|CS.state_bit_2~478 farmer|CS.state_bit_2~483 farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 1.000ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "start destination 10.000 ns - Shortest register " "Info: - Shortest clock path from clock \"start\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns start 1 CLK PIN_15 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 5; CLK Node = 'start'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "farmer.v" "" { Text "C:/altera/quartus60/win/farmer/farmer.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns farmer\|CS.state_bit_2 2 REG LC32 76 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer\|CS.state_bit_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { start start~out farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.000 ns" { in[0] farmer|CS.state_bit_2~478 farmer|CS.state_bit_2~483 farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.000 ns" { in[0] in[0]~out farmer|CS.state_bit_2~478 farmer|CS.state_bit_2~483 farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 1.000ns 1.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { start start~out farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "start out1\[1\] farmer\|CS.state_bit_2 32.000 ns register " "Info: tco from clock \"start\" to destination pin \"out1\[1\]\" through register \"farmer\|CS.state_bit_2\" is 32.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "start source 10.000 ns + Longest register " "Info: + Longest clock path from clock \"start\" to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns start 1 CLK PIN_15 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_15; Fanout = 5; CLK Node = 'start'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "farmer.v" "" { Text "C:/altera/quartus60/win/farmer/farmer.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns farmer\|CS.state_bit_2 2 REG LC32 76 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer\|CS.state_bit_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { start start~out farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.000 ns + Longest register pin " "Info: + Longest register to pin delay is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns farmer\|CS.state_bit_2 1 REG LC32 76 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 76; REG Node = 'farmer\|CS.state_bit_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { farmer|CS.state_bit_2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 10.000 ns WideOr2~39 2 COMB SEXP35 1 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP35; Fanout = 1; COMB Node = 'WideOr2~39'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { farmer|CS.state_bit_2 WideOr2~39 } "NODE_NAME" } } { "farmer.v" "" { Text "C:/altera/quartus60/win/farmer/farmer.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 17.000 ns WideOr2~40 3 COMB LC46 1 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 17.000 ns; Loc. = LC46; Fanout = 1; COMB Node = 'WideOr2~40'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { WideOr2~39 WideOr2~40 } "NODE_NAME" } } { "farmer.v" "" { Text "C:/altera/quartus60/win/farmer/farmer.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 21.000 ns out1\[1\] 4 PIN PIN_24 0 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 21.000 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'out1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.000 ns" { WideOr2~40 out1[1] } "NODE_NAME" } } { "farmer.v" "" { Text "C:/altera/quartus60/win/farmer/farmer.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "19.000 ns ( 90.48 % ) " "Info: Total cell delay = 19.000 ns ( 90.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 9.52 % ) " "Info: Total interconnect delay = 2.000 ns ( 9.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.000 ns" { farmer|CS.state_bit_2 WideOr2~39 WideOr2~40 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "21.000 ns" { farmer|CS.state_bit_2 WideOr2~39 WideOr2~40 out1[1] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 8.000ns 7.000ns 4.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { start farmer|CS.state_bit_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { start start~out farmer|CS.state_bit_2 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.000 ns" { farmer|CS.state_bit_2 WideOr2~39 WideOr2~40 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "21.000 ns" { farmer|CS.state_bit_2 WideOr2~39 WideOr2~40 out1[1] } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 8.000ns 7.000ns 4.000ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}