📄 farmer.fit.rpt
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; Number of Macrocells (Average = 3.38) ; Number of LABs (Total = 3) ;
+----------------------------------------+-----------------------------+
; 0 ; 5 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
; 2 ; 4 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.75) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
+-------------------------------------------------+-----------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; B ; LC23 ; farmer|CS.state_bit_3~401, farmer|CS.state_bit_1, farmer|CS.state_bit_3, in[2], farmer|CS.state_bit_2, in[0], farmer|CS.state_bit_0, in[1], in[3], farmer|CS.state_bit_4, start, reset ; CS.S8~60, farmer|CS.state_bit_3, farmer|CS.state_bit_4, farmer|CS.state_bit_1, farmer|CS.state_bit_0, WideOr4~5, WideOr0~57, WideOr0~63, farmer|CS.state_bit_2, WideOr1~40, WideOr2~34, WideOr2~35, WideOr2~36, WideOr2~37, WideOr2~39, WideOr3~40, WideOr3~47, WideOr2~47, WideOr1~47, farmer|CS.state_bit_3~401, farmer|CS.state_bit_4~462, farmer|CS.state_bit_4~465, farmer|CS.state_bit_1~1109, farmer|CS.state_bit_1~1112, farmer|CS.state_bit_0~755, farmer|CS.state_bit_2~478, farmer|CS.state_bit_2~483, WideOr2~48 ;
; B ; LC26 ; farmer|CS.state_bit_1~1112, farmer|CS.state_bit_2, in[1], farmer|CS.state_bit_1, in[2], farmer|CS.state_bit_3, in[0], farmer|CS.state_bit_0, in[3], farmer|CS.state_bit_4, start, reset ; CS.S8~60, farmer|CS.state_bit_3, farmer|CS.state_bit_4, farmer|CS.state_bit_1, farmer|CS.state_bit_0, WideOr4~5, WideOr0~57, WideOr0~63, farmer|CS.state_bit_2, WideOr1~40, WideOr2~34, WideOr2~35, WideOr2~37, WideOr3~40, WideOr3~47, WideOr2~47, WideOr1~47, farmer|CS.state_bit_3~401, farmer|CS.state_bit_4~462, farmer|CS.state_bit_4~465, farmer|CS.state_bit_1~1112, farmer|CS.state_bit_0~751, farmer|CS.state_bit_0~755, WideOr0~65, WideOr0~67, farmer|CS.state_bit_2~478, farmer|CS.state_bit_2~483, WideOr2~48 ;
; B ; LC29 ; farmer|CS.state_bit_0~755, in[1], in[2], in[3], farmer|CS.state_bit_2, farmer|CS.state_bit_0, in[0], farmer|CS.state_bit_3, farmer|CS.state_bit_1, farmer|CS.state_bit_4, start, reset ; farmer|CS.state_bit_3, farmer|CS.state_bit_4, farmer|CS.state_bit_1, farmer|CS.state_bit_0, WideOr4~5, WideOr0~57, WideOr0~63, farmer|CS.state_bit_2, WideOr1~40, WideOr2~37, WideOr2~38, WideOr2~39, WideOr3~40, WideOr3~47, WideOr2~47, WideOr1~47, farmer|CS.state_bit_3~401, farmer|CS.state_bit_4~462, farmer|CS.state_bit_4~465, farmer|CS.state_bit_1~1109, farmer|CS.state_bit_1~1112, farmer|CS.state_bit_0~751, farmer|CS.state_bit_0~755, WideOr0~65, WideOr0~67, farmer|CS.state_bit_2~478, farmer|CS.state_bit_2~483 ;
; B ; LC32 ; farmer|CS.state_bit_2~483, in[1], farmer|CS.state_bit_0, farmer|CS.state_bit_4, farmer|CS.state_bit_2, farmer|CS.state_bit_1, farmer|CS.state_bit_3, in[2], in[3], start, reset ; CS.S8~60, farmer|CS.state_bit_3, farmer|CS.state_bit_4, farmer|CS.state_bit_1, farmer|CS.state_bit_0, WideOr4~5, WideOr0~57, WideOr0~63, farmer|CS.state_bit_2, WideOr1~40, WideOr2~34, WideOr2~35, WideOr2~37, WideOr2~39, WideOr3~40, WideOr3~47, WideOr2~47, WideOr1~47, farmer|CS.state_bit_3~401, farmer|CS.state_bit_4~462, farmer|CS.state_bit_4~465, farmer|CS.state_bit_1~1109, farmer|CS.state_bit_1~1112, farmer|CS.state_bit_0~751, farmer|CS.state_bit_0~755, farmer|CS.state_bit_2~478, farmer|CS.state_bit_2~483, WideOr2~48 ;
; B ; LC17 ; farmer|CS.state_bit_4, farmer|CS.state_bit_0, farmer|CS.state_bit_2, farmer|CS.state_bit_3, farmer|CS.state_bit_1 ; out1[0] ;
; B ; LC19 ; farmer|CS.state_bit_4, farmer|CS.state_bit_0, farmer|CS.state_bit_2, farmer|CS.state_bit_3, farmer|CS.state_bit_1 ; out2[0] ;
; B ; LC21 ; WideOr2~48, farmer|CS.state_bit_1, farmer|CS.state_bit_2, farmer|CS.state_bit_3, farmer|CS.state_bit_4, farmer|CS.state_bit_0 ; out2[1] ;
; B ; LC22 ; farmer|CS.state_bit_1, farmer|CS.state_bit_3, in[2], farmer|CS.state_bit_2, farmer|CS.state_bit_0, in[1], in[3], in[0], farmer|CS.state_bit_4 ; farmer|CS.state_bit_3 ;
; B ; LC24 ; farmer|CS.state_bit_2, in[1], farmer|CS.state_bit_3, in[0], farmer|CS.state_bit_0, in[3], farmer|CS.state_bit_4, in[2] ; farmer|CS.state_bit_1~1112 ;
; B ; LC25 ; farmer|CS.state_bit_1~1109, farmer|CS.state_bit_2, in[1], farmer|CS.state_bit_1, farmer|CS.state_bit_3, in[0], farmer|CS.state_bit_0, in[3], farmer|CS.state_bit_4, in[2] ; farmer|CS.state_bit_1 ;
; B ; LC27 ; in[1], in[2], in[3], farmer|CS.state_bit_2, farmer|CS.state_bit_0, in[0], farmer|CS.state_bit_1 ; farmer|CS.state_bit_0~755 ;
; B ; LC28 ; farmer|CS.state_bit_0~751, in[1], in[2], in[3], farmer|CS.state_bit_2, farmer|CS.state_bit_0, in[0], farmer|CS.state_bit_3, farmer|CS.state_bit_4, farmer|CS.state_bit_1 ; farmer|CS.state_bit_0 ;
; B ; LC30 ; in[0], in[2], in[1], in[3], farmer|CS.state_bit_0, farmer|CS.state_bit_4, farmer|CS.state_bit_2, farmer|CS.state_bit_1, farmer|CS.state_bit_3 ; farmer|CS.state_bit_2~483 ;
; B ; LC31 ; farmer|CS.state_bit_2~478, in[0], in[2], in[1], in[3], farmer|CS.state_bit_0, farmer|CS.state_bit_2, farmer|CS.state_bit_1, farmer|CS.state_bit_3, farmer|CS.state_bit_4 ; farmer|CS.state_bit_2 ;
; B ; LC20 ; farmer|CS.state_bit_4, farmer|CS.state_bit_1, farmer|CS.state_bit_2, farmer|CS.state_bit_3 ; WideOr2~47 ;
; C ; LC38 ; WideOr0~65, farmer|CS.state_bit_4, farmer|CS.state_bit_1, farmer|CS.state_bit_2, farmer|CS.state_bit_3, farmer|CS.state_bit_0 ; out1[3] ;
; C ; LC40 ; WideOr0~67, farmer|CS.state_bit_4, farmer|CS.state_bit_1, farmer|CS.state_bit_2, farmer|CS.state_bit_3, farmer|CS.state_bit_0 ; out2[3] ;
; C ; LC43 ; farmer|CS.state_bit_1, farmer|CS.state_bit_3, farmer|CS.state_bit_2, farmer|CS.state_bit_0, farmer|CS.state_bit_4 ; out1[2] ;
; C ; LC46 ; WideOr2~34, WideOr2~35, WideOr2~36, WideOr2~37, WideOr2~38, WideOr2~39 ; out1[1] ;
; C ; LC45 ; farmer|CS.state_bit_1, farmer|CS.state_bit_3, farmer|CS.state_bit_2, farmer|CS.state_bit_0, farmer|CS.state_bit_4 ; out2[2] ;
; C ; LC37 ; farmer|CS.state_bit_4, farmer|CS.state_bit_1, farmer|CS.state_bit_0 ; WideOr0~57 ;
; C ; LC39 ; farmer|CS.state_bit_4, farmer|CS.state_bit_1, farmer|CS.state_bit_0 ; WideOr0~63 ;
; G ; LC104 ; farmer|CS.state_bit_2, farmer|CS.state_bit_3, farmer|CS.state_bit_4, farmer|CS.state_bit_1 ; ok ;
; G ; LC99 ; farmer|CS.state_bit_4~465, farmer|CS.state_bit_3, farmer|CS.state_bit_1, farmer|CS.state_bit_2, farmer|CS.state_bit_0, farmer|CS.state_bit_4, in[2], in[3], in[1], in[0], start, reset ; CS.S8~60, farmer|CS.state_bit_3, farmer|CS.state_bit_4, farmer|CS.state_bit_1, farmer|CS.state_bit_0, WideOr4~5, WideOr0~57, WideOr0~63, farmer|CS.state_bit_2, WideOr1~40, WideOr2~34, WideOr2~36, WideOr2~37, WideOr2~38, WideOr3~40, WideOr3~47, WideOr2~47, WideOr1~47, farmer|CS.state_bit_3~401, farmer|CS.state_bit_4~462, farmer|CS.state_bit_4~465, farmer|CS.state_bit_1~1109, farmer|CS.state_bit_1~1112, farmer|CS.state_bit_0~755, WideOr0~65, WideOr0~67, farmer|CS.state_bit_2~478, farmer|CS.state_bit_2~483, WideOr2~48 ;
; G ; LC101 ; farmer|CS.state_bit_2, farmer|CS.state_bit_3, farmer|CS.state_bit_4, farmer|CS.state_bit_1, farmer|CS.state_bit_0 ; e0 ;
; G ; LC97 ; farmer|CS.state_bit_3, farmer|CS.state_bit_1, farmer|CS.state_bit_2, farmer|CS.state_bit_0, farmer|CS.state_bit_4 ; farmer|CS.state_bit_4~465 ;
; G ; LC98 ; farmer|CS.state_bit_4~462, farmer|CS.state_bit_3, farmer|CS.state_bit_1, farmer|CS.state_bit_2, farmer|CS.state_bit_0, farmer|CS.state_bit_4, in[2], in[3], in[0], in[1] ; farmer|CS.state_bit_4 ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+-----------------------------------------+
; Option ; Setting ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving an unspecified signal ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+-----------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Wed Nov 28 19:22:56 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off farmer -c farmer
Info: Selected device EPM7128SLC84-15 for design "farmer"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Nov 28 19:23:01 2007
Info: Elapsed time: 00:00:06
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