📄 hostc_structure.htm
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<td><strong>Flag</strong></td>
<td><strong>Description</strong></td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_SUPPORTS_POWER</font></p>
</td>
<td>Host controller supports power management.</td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_BUS_1BIT</font></p>
</td>
<td>Host supports 1-bit mode (CMD/1-bit Data)</td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_BUS_4BIT</font></p>
</td>
<td>Host supports 4-bit mode (CMD/4-bit data), this applies to SD, SDIO and
MMC (4.0 or higher) cards.</td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_BUS_MMC8BIT</font></p>
</td>
<td>Host supports 8-bit mode (CMD/8-bit data),
this applies to MMC (4.0 or higher) cards.</td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_BUS_SPI</font></p>
</td>
<td>Host supports SPI mode.</td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_READ_WAIT</font></p>
</td>
<td>Host supports Read-Wait protocol (see SDIO spec).</td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_MULTI_BLK_IRQ</font></p>
</td>
<td>Host supports detecting interrupts during mult-block
transactions.</td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_SLOT_POLLING</font></p>
</td>
<td>Host requires slot polling for the detection of cards. The core
uses a helper task/thread that will periodically issue SD/SDIO
commands to the slot (roughly 1 second). A successful response
to any command indicates the presence of a card. Once a card
is initialized, the helper issues a command (roughly every 1
second) to poll the card's presence. </td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_POWER_SWITCH</font></p>
</td>
<td>Host supports power cycling (power FET switch
control). This flag indicates that the host can cycle
power to the slot. This is useful for entering/leaving SPI
mode operation. Cycling to SPI mode dynamically is reserved for
future use.</td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_NO_SPI_CRC</font></p>
</td>
<td>Host operates SPI mode without CRC checking. This enhances
host performance in generic SPI mode implementations.</td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_AUTO_CMD12</font></p>
</td>
<td>Host can issue CMD12 automatically to stop transmission during
multi-block reads/writes.</td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_NO_4BIT_IRQ</font></p>
</td>
<td>Host can support SD memory cards in 4 bit mode however, SDIO cards must
operate in 1 bit mode due to the lack of clock control for
interrupt detection in 4 bit mode.</td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_SD_HIGH_SPEED</font></p>
</td>
<td>Host supports SD Physical Specification 1.10 high speed mode. </td>
</tr>
<tr>
<td>
<p><font face="Courier New" size="2">SDHCD_ATTRIB_MMC_HIGH_SPEED</font></p>
</td>
<td>Host supports MMC high speed mode. In most cases, the host controller
can simply set his bit and let the busdriver use the higher
reported clock rates (up to 52Mhz). Only hosts that can
support the tighter I/O timming requirements for high speed
operation should set this bit.</td>
</tr>
</table>
<br>
<br>
<p class="BODYTEXT"><br>
<strong>SD/SDIO Bus Electrical Interface :</strong></p>
<p class="BODYTEXT">The HCD can report limitations to it's bus
interface. This includes limitations such as maximum clock rate
support and data transfer parameters such as bytes allowed per block
and blocks per transaction. Peripheral drivers can obtain these
limits and behave accordingly and not exceed the hardware's
capabilities. The host controller also indicates electrical
parameters (voltage, current) that require configuration by the
SDIO core and peripheral drivers. The host controller's
advertised <font face="Courier New">SlotVoltageCaps</font> is a bit
mask of supported voltage levels. The SD/SDIO initialization
sequence allows a host to negotiate an optimal slot voltage based
on card and host voltage capabilities. The host's <font
face="Courier New">SlotVoltagePreferred</font>, offers the SDIO core
a "hint" to a preferred voltage for maximum efficiency.
Each host controller can set a maximum slot current budget (<font
face="Courier New">MaxSlotCurrent</font>) that is managed by the
SDIO core . All SD/SDIO function drivers must allocate
slot current from this "pool" and can only proceed after the
request is satisfied.</p>
<p class="BODYTEXT">The following code demonstrates how the HCD
structure is initialized and registered:</p>
<pre>
SET_SDIO_STACK_VERSION(&pDeviceContext->Hcd);
pDeviceContext->Hcd.Attributes = SDHCD_ATTRIB_BUS_1BIT |
SDHCD_ATTRIB_BUS_4BIT |
SDHCD_ATTRIB_MULTI_BLK_IRQ |
SDHCD_ATTRIB_AUTO_CMD12 |
SDHCD_ATTRIB_POWER_SWITCH ;
pDeviceContext->Hcd.SlotNumber = 0;
pDeviceContext->Hcd.MaxBlocksPerTrans = 1023;
pDeviceContext->Hcd.MaxBytesPerBlock = 2048;
pDeviceContext->Hcd.MaxSlotCurrent = 300; // 300 mA
pDeviceContext->Hcd.MaxClockRate = 24000000; // 24Mhz
pDeviceContext->Hcd.SlotVoltageCaps = SLOT_POWER_3_3V | SLOT_POWER_1_8V;
pDeviceContext->Hcd.SlotVoltagePreferred = SLOT_POWER_3_3V;
// set our instance context
pDeviceContext->Hcd.pContext = pDeviceContext;
// setup callback pointers
pDeviceContext->Hcd.pRequest = HcdRequest;
pDeviceContext->Hcd.pConfigure = HcdConfig;
pDeviceContext->Hcd.pDevice = &pPCIdevice->dev;
// initialize hardware.....
// register host
if (!SDIO_SUCCESS((status = SDIO_RegisterHostController(&pDeviceContext->Hcd)))) {
.. failed
}
</pre>
<p><!-- InstanceEndEditable -->
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