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<font color="#FFFFFF" size="5" face="Arial, Helvetica, sans-serif"><strong>Embedded SDIO Driver Kit Help </strong></font></td>
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<p class="BODYTEXT"> <strong>HDK Topics:
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<td><a href="#pdkfaq1">I found in the HCD sample code that the driver has the possibility to enable/disable clock control after each request.
Why is the clock turned off? For example in wifi or bluetooth communication, does the device card always need a clock on it ?
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<td><a href="#pdkfaq2">I am developing a new host controller driver, I need to configure my hardware based on the command type (SD/MMC memory or SDIO command) , also
I need to know if the operation is suspending an outstanding command which will be resumed later (as per SDIO spec).
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<td><a href="#pdkfaq3">What clock rate should I use as a threshold for determining whether I should process a command/response operation using register polling?
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<td><a href="#pdkfaq4">What are the consequences of not implementing a mechanical switch for card insert detection? Is polling supported?</a></td>
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<p class="HEADING3"><strong><a name="pdkfaq1"></a>I found in the HCD sample code that the driver has the possibility to enable/disable clock control after each request.
Why is the clock turned off? For example in wifi or bluetooth communication, does the device card always need a clock on it ?
</strong></p>
<p class="BODYTEXT">
There is a common misconception that the SD or MMC clock drives card-side logic. This is not the case.
The clock is only used in communications. The SDIO card has to use its own clock for logic. The spec allows
for the host to remove the clock at any time to either pause communications or to reduce power.
In the sample code the clock is turned off only after the full transaction has completed.
The only exception to having the clock on all the time is for cards that use 4 bit interrupts.
Since the interrupt and the DATA1 line are shared, the card uses the clock to monitor the
state of the bus and only drive the interrupt line when the bus is idle and during block gaps.
If you look at the PCI ellen card driver, when the host requests 4-bit interrupt support,
the PCI ellen driver sets a flag to keep the clock active even when a transaction is complete.
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<p class="HEADING3"><strong><a name="pdkfaq2"></a>I am developing a new host controller driver, I need to configure my hardware based on the command type (SD/MMC memory or SDIO command) , also
I need to know if the operation is suspending an outstanding command which will be resumed later (as per SDIO spec).</strong></p>
<p class="BODYTEXT">If your controller needs information on whether it is a memory
or I/O command, you will need to put a switch statement in your hcdrequest
callback and check the command code.
Our architecture breaks down commands into its basic elements (command code,
argument, expected response, and data blocks) , this makes it more extensible
for new commands. If you need to know if it is a memory or SDIO command, you
will need to add your own
switch statement and check every command. For SDIO commands, CMD5,CMD52 and
CMD53 can be checked. Everything else would fall under SD/MMC commands.
As for I/O suspend/resume, the stack does not support this feature.
All bus commands must complete and cannot be preempted by other commands.
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<p class="HEADING3"><strong><a name="pdkfaq3"></a>What clock rate should I use as a threshold for determining whether I should process a command/response operation using register polling?</strong></p>
<p class="BODYTEXT">
5 Mhz is common in the provided driver samples. If you make it a module parameter,
your end users (developers) can ultimately decide for themselves. Generally
if
the command can take less than 25-40us, you
should use polling as the interrupt/context switch overhead can be greater than
that. For a command you have:
48 + (up to) 64 + (up to) 136 = ~248 bit times @ 5 mhz = ~50us.
On average this is probably more like 15-20 us, since most commands have just
a 48 bit response and most commands do not take the entire 64 clocks to respond.
You could take a more fine grained approach and calculate the number of response
bits and adjust accordingly. We've found that anything higher than 5Mhz clock
rate should be done with polling to save the
interrupt context switch time.
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<p class="HEADING3"><strong><a name="pdkfaq4"></a>What are the consequences of not implementing a mechanical switch for card insert detection? Is polling supported?</strong></p>
<p class="BODYTEXT">The bus driver can handle HCDs that require periodic polling
for card insertion or removal. The HCD simply has to indicate this in an HCD
atrribute bit.
Slot polling uses a command every 1 second to check for presence or removal.
The command issued is benign and is usually fetching the Card Version register
for SDIO
cards or the card status for SD/MMC cards. For many systems this is good enough
and the additional bus request every second does not impact driver performance.
However, for battery powered systems, this polling interval may prevent the
CPU from going
into full idle. Depending on how the system is designed, this may not have
any impact at all.</p>
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