📄 emac.lst
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\ 00000006 2000 MOVS R0,R4
\ 00000008 ........ BL AT91F_Enable_Mdi
158 read_phy(pEmac, AT91C_PHY_ADDR, MII_PHYSID1, &phyid1);
\ 0000000C 01AB ADD R3,SP,#+4
\ 0000000E 0222 MOVS R2,#+2
\ 00000010 1F21 MOVS R1,#+31
\ 00000012 2000 MOVS R0,R4
\ 00000014 ........ BL read_phy
159 read_phy(pEmac, AT91C_PHY_ADDR, MII_PHYSID2, &phyid2);
\ 00000018 6B46 MOV R3,SP
\ 0000001A 0322 MOVS R2,#+3
\ 0000001C 1F21 MOVS R1,#+31
\ 0000001E 2000 MOVS R0,R4
\ 00000020 ........ BL read_phy
160
161 /* AMD AM79C875: PHY_ID1 = 0x0022 PHY_ID2 = 0x5541
162 Bits 3:0 Revision Number Four bit manufacturer抯 revision number. 0001 stands for Rev. A, etc.
163 These bits are masked.
164 */
165 if (((phyid1 << 16) | (phyid2 & 0xfff0)) != MII_DM9161_ID) {
\ 00000024 0198 LDR R0,[SP, #+4]
\ 00000026 0004 LSLS R0,R0,#+16
\ 00000028 0099 LDR R1,[SP, #+0]
\ 0000002A 0C4A LDR R2,??AT91F_Ether_Probe_0 ;; 0xfff0
\ 0000002C 0A40 ANDS R2,R2,R1
\ 0000002E 0243 ORRS R2,R2,R0
\ 00000030 0B48 LDR R0,??AT91F_Ether_Probe_0+0x4 ;; 0x181b8a0
\ 00000032 8242 CMP R2,R0
\ 00000034 05D0 BEQ ??AT91F_Ether_Probe_1
166 AT91F_Disable_Mdi(pEmac);
\ 00000036 2000 MOVS R0,R4
\ 00000038 ........ BL AT91F_Disable_Mdi
167 return -1;
\ 0000003C 0020 MOVS R0,#+0
\ 0000003E C043 MVNS R0,R0 ;; #-1
\ 00000040 07E0 B ??AT91F_Ether_Probe_2
168 }
169 status = AT91F_GetLinkSpeed(pEmac);
\ ??AT91F_Ether_Probe_1:
\ 00000042 2000 MOVS R0,R4
\ 00000044 ........ BL AT91F_GetLinkSpeed
\ 00000048 0500 MOVS R5,R0
170 AT91F_Disable_Mdi(pEmac);
\ 0000004A 2000 MOVS R0,R4
\ 0000004C ........ BL AT91F_Disable_Mdi
171 return status;
\ 00000050 2800 MOVS R0,R5
\ ??AT91F_Ether_Probe_2:
\ 00000052 02B0 ADD SP,SP,#+8
\ 00000054 30BC POP {R4,R5}
\ 00000056 02BC POP {R1}
\ 00000058 0847 BX R1 ;; return
\ 0000005A C046 Nop
\ ??AT91F_Ether_Probe_0:
\ 0000005C F0FF0000 DC32 0xfff0
\ 00000060 A0B88101 DC32 0x181b8a0
172 }
173
174
175
176 //*----------------------------------------------------------------------------
177 //* \fn AT91F_EMACInit
178 //* \brief This function initialise the ethernet
179 //*----------------------------------------------------------------------------
\ In segment CODE, align 4, keep-with-next
180 int AT91F_EMACInit( // \return Status ( Success = 0)
181 AT91PS_EMAC pEmac, // \arg Pointer to AT91PS_EMAC service
182 unsigned int pRxTdList,
183 unsigned int pTxTdList)
184 {
\ AT91F_EMACInit:
\ 00000000 70B5 PUSH {R4-R6,LR}
\ 00000002 0400 MOVS R4,R0
\ 00000004 0D00 MOVS R5,R1
\ 00000006 1600 MOVS R6,R2
185 if (AT91F_Ether_Probe(pEmac))
\ 00000008 2000 MOVS R0,R4
\ 0000000A ........ BL AT91F_Ether_Probe
\ 0000000E 0028 CMP R0,#+0
\ 00000010 02D0 BEQ ??AT91F_EMACInit_0
186 return -1;
\ 00000012 0020 MOVS R0,#+0
\ 00000014 C043 MVNS R0,R0 ;; #-1
\ 00000016 24E0 B ??AT91F_EMACInit_1
187
188 // the sequence write EMAC_SA1L and write EMAC_SA1H must be respected
189 pEmac->EMAC_SA1L = ((int)OurEmacAddr[3] << 24) | ((int)OurEmacAddr[2] << 16) | ((int)OurEmacAddr[1] << 8) | OurEmacAddr[0];
\ ??AT91F_EMACInit_0:
\ 00000018 9820 MOVS R0,#+152
\ 0000001A 1349 LDR R1,??AT91F_EMACInit_2 ;; OurEmacAddr + 3
\ 0000001C 0978 LDRB R1,[R1, #+0]
\ 0000001E 0A06 LSLS R2,R1,#+24
\ 00000020 1249 LDR R1,??AT91F_EMACInit_2+0x4 ;; OurEmacAddr + 2
\ 00000022 0978 LDRB R1,[R1, #+0]
\ 00000024 0904 LSLS R1,R1,#+16
\ 00000026 1143 ORRS R1,R1,R2
\ 00000028 114A LDR R2,??AT91F_EMACInit_2+0x8 ;; OurEmacAddr + 1
\ 0000002A 1278 LDRB R2,[R2, #+0]
\ 0000002C 1202 LSLS R2,R2,#+8
\ 0000002E 0A43 ORRS R2,R2,R1
\ 00000030 .... LDR R1,??DataTable0 ;; OurEmacAddr
\ 00000032 0978 LDRB R1,[R1, #+0]
\ 00000034 1143 ORRS R1,R1,R2
\ 00000036 2150 STR R1,[R4, R0]
190 pEmac->EMAC_SA1H = ((int)OurEmacAddr[5] << 8) | OurEmacAddr[4];
\ 00000038 9C20 MOVS R0,#+156
\ 0000003A 0E49 LDR R1,??AT91F_EMACInit_2+0xC ;; OurEmacAddr + 5
\ 0000003C 0978 LDRB R1,[R1, #+0]
\ 0000003E 0902 LSLS R1,R1,#+8
\ 00000040 0D4A LDR R2,??AT91F_EMACInit_2+0x10 ;; OurEmacAddr + 4
\ 00000042 1278 LDRB R2,[R2, #+0]
\ 00000044 0A43 ORRS R2,R2,R1
\ 00000046 2250 STR R2,[R4, R0]
191
192 pEmac->EMAC_RBQP = pRxTdList;
\ 00000048 A561 STR R5,[R4, #+24]
193 pEmac->EMAC_TBQP = pTxTdList;
\ 0000004A E661 STR R6,[R4, #+28]
194
195 //Clear receive status register
196 pEmac->EMAC_RSR = (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
\ 0000004C 0720 MOVS R0,#+7
\ 0000004E 2062 STR R0,[R4, #+32]
197 pEmac->EMAC_NCFGR |= (AT91C_EMAC_CAF | AT91C_EMAC_NBC );// | AT91C_EMAC_RBOF_OFFSET_2);
\ 00000050 6068 LDR R0,[R4, #+4]
\ 00000052 3021 MOVS R1,#+48
\ 00000054 0143 ORRS R1,R1,R0
\ 00000056 6160 STR R1,[R4, #+4]
198
199 pEmac->EMAC_NCR |= (AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT);
\ 00000058 2068 LDR R0,[R4, #+0]
\ 0000005A 8C21 MOVS R1,#+140
\ 0000005C 0143 ORRS R1,R1,R0
\ 0000005E 2160 STR R1,[R4, #+0]
200
201 return 0;
\ 00000060 0020 MOVS R0,#+0
\ ??AT91F_EMACInit_1:
\ 00000062 70BC POP {R4-R6}
\ 00000064 02BC POP {R1}
\ 00000066 0847 BX R1 ;; return
\ ??AT91F_EMACInit_2:
\ 00000068 ........ DC32 OurEmacAddr + 3
\ 0000006C ........ DC32 OurEmacAddr + 2
\ 00000070 ........ DC32 OurEmacAddr + 1
\ 00000074 ........ DC32 OurEmacAddr + 5
\ 00000078 ........ DC32 OurEmacAddr + 4
202 }
203
204 #define AT91C_RCV_OFFSET 0
205
206 //*----------------------------------------------------------------------------
207 //* \fn AT91F_EmacEntry
208 //* \brief Initialise Emac to receive packets
209 //*----------------------------------------------------------------------------
\ In segment CODE, align 4, keep-with-next
210 int AT91F_EmacEntry(void)
211 {
\ AT91F_EmacEntry:
\ 00000000 30B5 PUSH {R4,R5,LR}
212 unsigned int i;
213 unsigned int val;
214
215 // Initialise RxtdList descriptor
216 for (i = 0; i < NB_RX_BUFFERS; ++i) {
\ 00000002 0020 MOVS R0,#+0
\ 00000004 0400 MOVS R4,R0
\ ??AT91F_EmacEntry_0:
\ 00000006 642C CMP R4,#+100
\ 00000008 15D2 BCS ??AT91F_EmacEntry_1
217 val = (unsigned int)(RxPacket + (i * ETH_RX_BUFFER_SIZE));
\ 0000000A 8020 MOVS R0,#+128
\ 0000000C 6043 MULS R0,R4,R0
\ 0000000E 2749 LDR R1,??AT91F_EmacEntry_2 ;; RxPacket
\ 00000010 0968 LDR R1,[R1, #+0]
\ 00000012 0818 ADDS R0,R1,R0
\ 00000014 0500 MOVS R5,R0
218 RxtdList[i].addr = val & 0xFFFFFFF8;
\ 00000016 0820 MOVS R0,#+8
\ 00000018 6043 MULS R0,R4,R0
\ 0000001A .... LDR R1,??DataTable10 ;; RxtdList
\ 0000001C 0968 LDR R1,[R1, #+0]
\ 0000001E EA08 LSRS R2,R5,#+3
\ 00000020 D200 LSLS R2,R2,#+3
\ 00000022 0A50 STR R2,[R1, R0]
219 RxtdList[i].U_Status.status = 0;
\ 00000024 0820 MOVS R0,#+8
\ 00000026 6043 MULS R0,R4,R0
\ 00000028 .... LDR R1,??DataTable10 ;; RxtdList
\ 0000002A 0968 LDR R1,[R1, #+0]
\ 0000002C 0818 ADDS R0,R1,R0
\ 0000002E 0021 MOVS R1,#+0
\ 00000030 4160 STR R1,[R0, #+4]
220 }
\ 00000032 641C ADDS R4,R4,#+1
\ 00000034 E7E7 B ??AT91F_EmacEntry_0
221 // Set the WRAP bit at the end of the list descriptor
222 RxtdList[NB_RX_BUFFERS-1].addr |= 0x02;
\ ??AT91F_EmacEntry_1:
\ 00000036 C620 MOVS R0,#+198
\ 00000038 8000 LSLS R0,R0,#+2 ;; #+792
\ 0000003A .... LDR R1,??DataTable10 ;; RxtdList
\ 0000003C 0968 LDR R1,[R1, #+0]
\ 0000003E C622 MOVS R2,#+198
\ 00000040 9200 LSLS R2,R2,#+2 ;; #+792
\ 00000042 .... LDR R3,??DataTable10 ;; RxtdList
\ 00000044 1B68 LDR R3,[R3, #+0]
\ 00000046 9A58 LDR R2,[R3, R2]
\ 00000048 0223 MOVS R3,#+2
\ 0000004A 1343 ORRS R3,R3,R2
\ 0000004C 0B50 STR R3,[R1, R0]
223
224 // Initialise TxtdList descriptor
225 for (i = 0; i < NB_TX_BUFFERS; ++i) {
\ 0000004E 0020 MOVS R0,#+0
\ 00000050 0400 MOVS R4,R0
\ ??AT91F_EmacEntry_3:
\ 00000052 022C CMP R4,#+2
\ 00000054 16D2 BCS ??AT91F_EmacEntry_4
226 val = (unsigned int)(TxPacket + (i * ETH_TX_BUFFER_SIZE));
\ 00000056 C020 MOVS R0,#+192
\ 00000058 C000 LSLS R0,R0,#+3 ;; #+1536
\ 0000005A 6043 MULS R0,R4,R0
\ 0000005C 1449 LDR R1,??AT91F_EmacEntry_2+0x4 ;; TxPacket
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