📄 emac.lst
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##############################################################################
# #
# IAR ARM ANSI C/C++ Compiler V4.40A/W32 EVALUATION 29/Feb/2008 22:29:23 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = interwork #
# Endian = little #
# Stack alignment = 4 #
# Source file = C:\AT91SAM7X256-BasicEmac-IAR4_30A-1_21\AT91SAM7X-Ba #
# sicEmac\src\Emac.c #
# Command line = C:\AT91SAM7X256-BasicEmac-IAR4_30A-1_21\AT91SAM7X-Ba #
# sicEmac\src\Emac.c -D ESS -lC #
# C:\AT91SAM7X256-BasicEmac-IAR4_30A-1_21\AT91SAM7X-Ba #
# sicEmac\compil\RAM_Debug\List\ -o #
# C:\AT91SAM7X256-BasicEmac-IAR4_30A-1_21\AT91SAM7X-Ba #
# sicEmac\compil\RAM_Debug\Obj\ -z2 --no_cse #
# --no_unroll --no_inline --no_code_motion --no_tbaa #
# --no_clustering --no_scheduling --debug --cpu_mode #
# thumb --endian little --cpu ARM7TDMI --stack_align #
# 4 --interwork -e --fpu None --dlib_config #
# "C:\Program Files\ARM\IAR Systems\Embedded #
# Workbench 4.0 Evaluation\ARM\LIB\dl4tptinl8n.h" -I #
# C:\AT91SAM7X256-BasicEmac-IAR4_30A-1_21\AT91SAM7X-Ba #
# sicEmac\compil\srciar\ -I #
# C:\AT91SAM7X256-BasicEmac-IAR4_30A-1_21\AT91SAM7X-Ba #
# sicEmac\compil\..\..\ -I "C:\Program Files\ARM\IAR #
# Systems\Embedded Workbench 4.0 Evaluation\ARM\INC\" #
# List file = C:\AT91SAM7X256-BasicEmac-IAR4_30A-1_21\AT91SAM7X-Ba #
# sicEmac\compil\RAM_Debug\List\Emac.lst #
# Object file = C:\AT91SAM7X256-BasicEmac-IAR4_30A-1_21\AT91SAM7X-Ba #
# sicEmac\compil\RAM_Debug\Obj\Emac.r79 #
# #
# #
##############################################################################
C:\AT91SAM7X256-BasicEmac-IAR4_30A-1_21\AT91SAM7X-BasicEmac\src\Emac.c
1 //*----------------------------------------------------------------------------
2 //* ATMEL Microcontroller Software Support - ROUSSET -
3 //*----------------------------------------------------------------------------
4 //* The software is delivered "AS IS" without warranty or condition of any
5 //* kind, either express, implied or statutory. This includes without
6 //* limitation any warranty or condition with respect to merchantability or
7 //* fitness for any particular purpose, or against the infringements of
8 //* intellectual property rights of others.
9 //*----------------------------------------------------------------------------
10 //* File Name : main.c
11 //* Object : main application written in C
12 //* Creation : Hi 11/18/2002
13 //* Update : JGe 08/02/2005 : SAM7X port
14 //*----------------------------------------------------------------------------
15
16 #include "board.h"
17 #include "Emac.h"
18 #include "mii.h"
19 #include <string.h>
20 #include <stdio.h>
21
22 //extern unsigned int AT91F_GetTickCount(void);
23 extern void AT91F_DBGU_Printk(char *buffer);
24 extern void AT91F_DisplayIpPacket(AT91PS_IPheader pIpHeader);
25 extern char MsgBuffer[256];
26 extern int AT91F_ProcessEmacPacket(AT91PS_IPheader pHeader);
27 extern void LED_TurnOn(unsigned int led);
28 extern void LED_TurnOff(unsigned int led);
29
30 // Our Ethernet MAC address and IP address
\ In segment DATA_I, align 4, align-sorted
31 char OurEmacAddr[6] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06};
\ OurEmacAddr:
\ 00000000 DS8 8
\ 00000008 REQUIRE `?<Initializer for OurEmacAddr>`
\ In segment DATA_I, align 4, align-sorted
32 unsigned char OurIpAddr[4] = {10, 159, 245, 183}; // {0x0A, 0xD7, 0xF5, 0xAC}
\ OurIpAddr:
\ 00000000 DS8 4
\ 00000004 REQUIRE `?<Initializer for OurIpAddr>`
33
34 //Buffer descriptor address must be word aligned
35 #define AT91C_EMAC_RX_TDLIST_BASE 0x00204000 // take care that RxtdList[NB_RCV_BUFFERS] area is available
36 #define AT91C_EMAC_TX_TDLIST_BASE (AT91C_EMAC_RX_TDLIST_BASE + NB_RX_BUFFERS * sizeof(AT91S_RxTdDescriptor))
37 #define AT91C_EMAC_RX_PACKET_BASE (AT91C_EMAC_TX_TDLIST_BASE + NB_TX_BUFFERS * sizeof(AT91S_TxTdDescriptor))
38 #define AT91C_EMAC_TX_PACKET_BASE (AT91C_EMAC_RX_PACKET_BASE + NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE)
39
\ In segment DATA_I, align 4, align-sorted
40 char *RxPacket = (char *)AT91C_EMAC_RX_PACKET_BASE;
\ RxPacket:
\ 00000000 DS8 4
\ 00000004 REQUIRE `?<Initializer for RxPacket>`
\ In segment DATA_I, align 4, align-sorted
41 char *TxPacket = (char *)AT91C_EMAC_TX_PACKET_BASE;
\ TxPacket:
\ 00000000 DS8 4
\ 00000004 REQUIRE `?<Initializer for TxPacket>`
\ In segment DATA_I, align 4, align-sorted
42 AT91PS_RxTdDescriptor RxtdList = (AT91PS_RxTdDescriptor) AT91C_EMAC_RX_TDLIST_BASE;
\ RxtdList:
\ 00000000 DS8 4
\ 00000004 REQUIRE `?<Initializer for RxtdList>`
\ In segment DATA_I, align 4, align-sorted
43 AT91PS_TxTdDescriptor TxtdList = (AT91PS_TxTdDescriptor)AT91C_EMAC_TX_TDLIST_BASE;
\ TxtdList:
\ 00000000 DS8 4
\ 00000004 REQUIRE `?<Initializer for TxtdList>`
44
\ In segment DATA_Z, align 4, align-sorted
45 unsigned int TxBuffIndex = 0;
\ TxBuffIndex:
\ 00000000 DS8 4
46
47 // mapping
48 // 0x00204000 - 0x0020431F : RX descriptor list : 800 bytes
49 // 0x00204320 - 0x0020432F : TX descriptor list : 16 bytes
50 // 0x00204330 - 0x0020752F : RX packets : 12800 bytes
51 // 0x00207530 - 0x0020762F : TX packets : 256 bytes
52
53 // ****************************************************************************************************
54 // ** EMAC lowlevel functions
55 // ****************************************************************************************************
56
57 // Enable the MDIO bit in MAC control register
\ In segment CODE, align 4, keep-with-next
58 void AT91F_Enable_Mdi(AT91PS_EMAC pEmac)
59 {
60 pEmac->EMAC_NCR |= AT91C_EMAC_MPE; // enable management port
\ AT91F_Enable_Mdi:
\ 00000000 0168 LDR R1,[R0, #+0]
\ 00000002 1022 MOVS R2,#+16
\ 00000004 0A43 ORRS R2,R2,R1
\ 00000006 0260 STR R2,[R0, #+0]
61 pEmac->EMAC_NCFGR |= (2)<<10; // MDC = MCK/32
\ 00000008 4168 LDR R1,[R0, #+4]
\ 0000000A 8022 MOVS R2,#+128
\ 0000000C 1201 LSLS R2,R2,#+4 ;; #+2048
\ 0000000E 0A43 ORRS R2,R2,R1
\ 00000010 4260 STR R2,[R0, #+4]
62 }
\ 00000012 7047 BX LR ;; return
63
64 // Disable the MDIO bit in the MAC control register
\ In segment CODE, align 4, keep-with-next
65 void AT91F_Disable_Mdi(AT91PS_EMAC pEmac)
66 {
67 pEmac->EMAC_NCR &= ~AT91C_EMAC_MPE; // disable management port
\ AT91F_Disable_Mdi:
\ 00000000 0168 LDR R1,[R0, #+0]
\ 00000002 1022 MOVS R2,#+16
\ 00000004 9143 BICS R1,R1,R2
\ 00000006 0160 STR R1,[R0, #+0]
68 }
\ 00000008 7047 BX LR ;; return
69
70 // Write value to the a PHY register
71 // Note: MDI interface is assumed to already have been enabled.
\ In segment CODE, align 4, keep-with-next
72 void write_phy(AT91PS_EMAC pEmac, unsigned char phy_addr, unsigned char address, unsigned int value)
73 {
\ write_phy:
\ 00000000 30B5 PUSH {R4,R5,LR}
74 pEmac->EMAC_MAN = ((AT91C_EMAC_SOF & (0x01<<30)) | (2 << 16) | (1 << 28)
75 | ((phy_addr & 0x1f) << 23) | (address << 18)) | (value & 0xffff);
\ 00000002 0906 LSLS R1,R1,#+24 ;; ZeroExtS R1,R1,#+24,#+24
\ 00000004 090E LSRS R1,R1,#+24
\ 00000006 CC06 LSLS R4,R1,#+27 ;; ZeroExtS R4,R1,#+27,#+27
\ 00000008 E40E LSRS R4,R4,#+27
\ 0000000A E405 LSLS R4,R4,#+23
\ 0000000C 1206 LSLS R2,R2,#+24 ;; ZeroExtS R2,R2,#+24,#+24
\ 0000000E 120E LSRS R2,R2,#+24
\ 00000010 9504 LSLS R5,R2,#+18
\ 00000012 2543 ORRS R5,R5,R4
\ 00000014 1C04 LSLS R4,R3,#+16 ;; ZeroExtS R4,R3,#+16,#+16
\ 00000016 240C LSRS R4,R4,#+16
\ 00000018 2C43 ORRS R4,R4,R5
\ 0000001A 044D LDR R5,??write_phy_0 ;; 0x50020000
\ 0000001C 2543 ORRS R5,R5,R4
\ 0000001E 4563 STR R5,[R0, #+52]
76
77 /* Wait until IDLE bit in Network Status register is cleared */
78 while (!(pEmac->EMAC_NSR & AT91C_EMAC_IDLE));
\ ??write_phy_1:
\ 00000020 8468 LDR R4,[R0, #+8]
\ 00000022 6407 LSLS R4,R4,#+29
\ 00000024 FCD5 BPL ??write_phy_1
79 }
\ 00000026 30BC POP {R4,R5}
\ 00000028 01BC POP {R0}
\ 0000002A 0047 BX R0 ;; return
\ ??write_phy_0:
\ 0000002C 00000250 DC32 0x50020000
80
81 // Read value stored in a PHY register.
82 // Note: MDI interface is assumed to already have been enabled.
\ In segment CODE, align 4, keep-with-next
83 void read_phy(AT91PS_EMAC pEmac, unsigned char phy_addr, unsigned char address, unsigned int *value)
84 {
\ read_phy:
\ 00000000 30B5 PUSH {R4,R5,LR}
85 pEmac->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30)) | (2 << 16) | (2 << 28)
86 | ((phy_addr & 0x1f) << 23) | (address << 18);
\ 00000002 0906 LSLS R1,R1,#+24 ;; ZeroExtS R1,R1,#+24,#+24
\ 00000004 090E LSRS R1,R1,#+24
\ 00000006 CC06 LSLS R4,R1,#+27 ;; ZeroExtS R4,R1,#+27,#+27
\ 00000008 E40E LSRS R4,R4,#+27
\ 0000000A E405 LSLS R4,R4,#+23
\ 0000000C 1206 LSLS R2,R2,#+24 ;; ZeroExtS R2,R2,#+24,#+24
\ 0000000E 120E LSRS R2,R2,#+24
\ 00000010 9504 LSLS R5,R2,#+18
\ 00000012 2543 ORRS R5,R5,R4
\ 00000014 064C LDR R4,??read_phy_0 ;; 0x60020000
\ 00000016 2C43 ORRS R4,R4,R5
\ 00000018 4463 STR R4,[R0, #+52]
87
88 /* Wait until IDLE bit in Network Status register is cleared */
89 while (!(pEmac->EMAC_NSR & AT91C_EMAC_IDLE));
\ ??read_phy_1:
\ 0000001A 8468 LDR R4,[R0, #+8]
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